System Configuration 0

Name:
SYSCFG0
Offset:
0x05
Reset:
0xC4
Access:
-
Bit76543210
CRCSRC[1:0]RSTPINCFG[1:0]EESAVE
AccessRRRRR
Reset11010

Bits 7:6 – CRCSRC[1:0]: CRC Source

CRC Source

See the CRC description for more information about the functionality.
ValueNameDescription
00 FLASH CRC of full Flash (boot, application code and application data)
01 BOOT CRC of the boot section
10 BOOTAPP CRC of application code and boot sections
11 NOCRC No CRC

Bits 3:2 – RSTPINCFG[1:0]: Reset Pin Configuration

Reset Pin Configuration

These bits select the Reset/UPDI pin configuration.
Note: When configuring the Reset Pin as GPIO, there is a potential conflict between the GPIO actively driving the output, and a 12V UPDI enable sequence initiation. To avoid this, the GPIO output driver is disabled for 768 OSC32K cycles after a System Reset. Enable any interrupts for this pin only after this period.
ValueDescription
0x0 GPIO
0x1 UPDI
0x2 RESET
0x3 Reserved

Bit 0 – EESAVE: EEPROM Save During Chip Erase

EEPROM Save During Chip Erase

If the device is locked, the EEPROM is always erased by a chip erase, regardless of this bit.
ValueDescription
0 EEPROM erased during chip erase
1 EEPROM not erased under chip erase