Interrupt Flags
Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPT | |||||||
Access | R/W | ||||||
Reset | 0 |
Interrupt Flag
This bit is set when an interrupt occurs. The interrupt conditions are dependent on the Counter Mode (CNTMODE) in TCBn.CTRLB.
This bit is cleared by writing a '1' to it or when the Capture register is read in Capture mode.
Counter Mode | Interrupt Set Condition |
---|---|
Periodic Interrupt mode | Set when the counter reaches TOP |
Timeout Check mode | Set when the counter reaches TOP |
Input Capture on Event mode | Set when an event occurs and the Capture register is loaded, flag clears when capture is read |
Input Capture Frequency Measurement mode | Set on edge when the Capture register is loaded and count initialized, flag clears when capture is read |
Input Capture Pulse-Width Measurement mode | Set on a edge when the Capture register is loaded, previous edge initialized the count, flag clears when capture is read |
Input Capture Frequency and Pulse-Width Measurement mode | Set on second (positive or negative) edge when the counter is stopped, flag clears when capture is read |
Single-Shot mode | Set when counter reaches TOP |
8-Bit PWM mode | Set when the counter reaches CCH |