Silicon Issue Summary

Legend
-
Erratum is not applicable.
X
Erratum is applicable.
*
This silicon revision was never released to production.
Peripheral Short Description Valid for Silicon Revision
ATtiny1616 ATtiny3216
Rev. A Rev. A Rev. B Rev. C
AC AC Interrupt Flag Not Set Unless Interrupt is Enabled X * * -
False Triggers May Occur Under Certain Conditions X * * -
False Triggering When Sweeping Negative Input of the AC When the Low-Power Mode is Disabled X * * -
ADC SAMPDLY and ASDV Does Not Work Together With SAMPLEN X * * -
Pending Event Stuck When Disabling the ADC X * * -
ADC Functionality Cannot be Ensured with CLKADC Above 1.5 MHz and a Setting of 25% Duty Cycle X * * X
ADC Performance Degrades with CLKADC Above 1.5 MHz and VDD < 2.7V X * * X
ADC Interrupt Flags Cleared When Reading RESH X * * -
Changing ADC Control Bits During Free-Running Mode not Working X * * -
One Extra Measurement Performed After Disabling ADC Free-Running Mode X * * X
ADC Wake-Up with WCOMP X * * -
CCL Connecting LUTs in Linked Mode Require OUTEN Set to ‘1’ X * * -
D-latch is Not Functional X * * -
RTC Any Write to the RTC.CTRLA Register Resets the RTC and PIT Prescaler X * * -
Disabling the RTC Stops the PIT X * * -
TCB Minimum Event Duration Must Exceed the Selected Clock Period X * * X
The TCB Interrupt Flag is Cleared When Reading CCMPH X * * -
TCB Input Capture Frequency and Pulse-Width Measurement Mode Not Working with Prescaled Clock X * * -
The TCA Restart Command Does Not Force a Restart of TCB X * * X
TCD TCD Event Output Lines May Give False Events X * * -
TCD Auto-Update Not Working X * * -
TWI TIMEOUT Bits in the TWI.MCTRLB Register are Not Accessible X * * -
TWI Master Mode Wrongly Detects the Start Bit as a Stop Bit X * * -
TWI Smart Mode Gives Extra Clock Pulse X * * -
The TWI Master Enable Quick Command is Not Accessible X * * -
USART TXD Pin Override Not Released When Disabling the Transmitter X * * X
Frame Error on a Previous Message May Cause False Start Bit Detection X * * -