ADC Performance Degrades with CLKADC Above 1.5 MHz and VDD < 2.7V

The ADC INL performance degrades if CLKADC > 1.5 MHz and ADCn.CALIB.DUTYCYC set to ‘0’ for VDD < 2.7V.

Work around

None.

Affected Silicon Revisions

ATtiny1617
Rev. A            
X            
ATtiny3217
Rev. A Rev. B Rev. C          
X * X