Instruction Set Summary

Several updates of the AVR CPU during its lifetime has resulted in different flavors of the instruction set, especially for the timing of the instructions. Machine code level of compatibility is intact for all CPU versions with a very few exceptions related to the Reduced Core (AVRrc), though not all instructions are included in the instruction set for all devices. The table below contains the major versions of the AVR 8-bit CPUs. In addition to the different versions, there are differences dependent of the size of the device memory map. Typically these differences are handled by a C/EC++ compiler, but users that are porting code should be aware that the code execution can vary slightly in number of clock cycles.

Table 1. Versions of AVR 8-bit CPU
Name Device Series Description
AVR AT90 Original instruction set from 1995.
AVRe megaAVR® Multiply (xMULxx), Move Word (MOVW), and enhanced Load Program Memory (LPM) added to the AVR instruction set. No timing differences.
AVRe tinyAVR® Multiply not included, but else equal to AVRe for megaAVR.
AVRxm XMEGA® Significantly different timing compared to AVR(e). The Read Modify Write (RMW) and DES encryption instructions are unique to this version.
AVRxt (AVR) AVR 2016 and onwards. This variant is based on AVRe and AVRxm. Closer related to AVRe, but with improved timing.
AVRrc tinyAVR The Reduced Core AVR CPU was developed for ultra-low pinout (6-pin) size constrained devices. The AVRrc therefore only has a 16 registers register-file (R31-R16) and a limited instruction set.
Table 2. Arithmetic and Logic Instructions
Mnemonic Operands Description   Op   Flags #Clocks AVR #Clocks AVRxm #Clocks AVRxt #Clocks AVRrc
ADD Rd, Rr Add without Carry Rd Rd + Rr Z,C,N,V,S,H 1 1 1 1
ADC Rd, Rr Add with Carry Rd Rd + Rr + C Z,C,N,V,S,H 1 1 1 1
ADIW Rd, K Add Immediate to Word Rd Rd + 1:Rd + K Z,C,N,V,S 2 2 2 N/A
SUB Rd, Rr Subtract without Carry Rd Rd - Rr Z,C,N,V,S,H 1 1 1 1
SUBI Rd, K Subtract Immediate Rd Rd - K Z,C,N,V,S,H 1 1 1 1
SBC Rd, Rr Subtract with Carry Rd Rd - Rr - C Z,C,N,V,S,H 1 1 1 1
SBCI Rd, K Subtract Immediate with Carry Rd Rd - K - C Z,C,N,V,S,H 1 1 1 1
SBIW Rd, K Subtract Immediate from Word Rd + 1:Rd Rd + 1:Rd - K Z,C,N,V,S 2 2 2 N/A
AND Rd, Rr Logical AND Rd Rd • Rr Z,N,V,S 1 1 1 1
ANDI Rd, K Logical AND with Immediate Rd Rd • K Z,N,V,S 1 1 1 1
OR Rd, Rr Logical OR Rd Rd v Rr Z,N,V,S 1 1 1 1
ORI Rd, K Logical OR with Immediate Rd Rd v K Z,N,V,S 1 1 1 1
EOR Rd, Rr Exclusive OR Rd Rd ⊕ Rr Z,N,V,S 1 1 1 1
COM Rd One’s Complement Rd $FF - Rd Z,C,N,V,S 1 1 1 1
NEG Rd Two’s Complement Rd $00 - Rd Z,C,N,V,S,H 1 1 1 1
SBR Rd,K Set Bit(s) in Register Rd Rd v K Z,N,V,S 1 1 1 1
CBR Rd,K Clear Bit(s) in Register Rd Rd • ($FFh - K) Z,N,V,S 1 1 1 1
INC Rd Increment Rd Rd + 1 Z,N,V,S 1 1 1 1
DEC Rd Decrement Rd Rd - 1 Z,N,V,S 1 1 1 1
TST Rd Test for Zero or Minus Rd Rd • Rd Z,N,V,S 1 1 1 1
CLR Rd Clear Register Rd Rd ⊕ Rd Z,N,V,S 1 1 1 1
SER Rd Set Register Rd $FF None 1 1 1 1
MUL Rd,Rr Multiply Unsigned R1:R0 Rd x Rr (UU) Z,C 2 2 2 N/A
MULS Rd,Rr Multiply Signed R1:R0 Rd x Rr (SS) Z,C 2 2 2 N/A
MULSU Rd,Rr Multiply Signed with Unsigned R1:R0 Rd x Rr (SU) Z,C 2 2 2 N/A
FMUL Rd,Rr Fractional Multiply Unsigned R1:R0 Rd x Rr<<1 (UU) Z,C 2 2 2 N/A
FMULS Rd,Rr Fractional Multiply Signed R1:R0 Rd x Rr<<1 (SS) Z,C 2 2 2 N/A
FMULSU Rd,Rr Fractional Multiply Signed with Unsigned R1:R0 Rd x Rr<<1 (SU) Z,C 2 2 2 N/A
DES K Data Encryption

if (H = 0) then R15:R0

else if (H = 1) then R15:R0

Encrypt(R15:R0, K)

Decrypt(R15:R0, K)

  N/A 1/2 N/A N/A
Table 3. Branch Instructions
Mnemonic Operands Description   Op   Flags #Clocks AVR #Clocks AVRxm #Clocks AVRxt #Clocks AVRrc
RJMP k Relative Jump PC PC + k + 1 None 2 2 2 2
IJMP   Indirect Jump to (Z)

PC(15:0)

PC(21:16)

←


Z

0

None 2 2 2 2
EIJMP   Extended Indirect Jump to (Z)

PC(15:0)

PC(21:16)

←


Z

EIND

None 2 2 2 N/A
JMP k Jump PC k None 3 3 3 N/A
RCALL k Relative Call Subroutine PC PC + k + 1 None 3 / 4(1) 2 / 3(1) 2 / 3 3(1)
ICALL   Indirect Call to (Z)

PC(15:0)

PC(21:16)

←


Z

0

None 3 / 4(1) 2 / 3(1) 2 / 3 3(1)
EICALL   Extended Indirect Call to (Z)

PC(15:0)

PC(21:16)

←


Z

EIND

None 4(1) 3(1) 2 / 3 N/A
CALL k Call Subroutine PC k None 4 / 5(1) 3 / 4(1) 3 / 4 N/A
RET   Subroutine Return PC STACK None 4 / 5(1) 4 / 5(1) 4 / 5 6(1)
RETI   Interrupt Return PC STACK I 4 / 5(1) 4 / 5(1) 4 / 5 6(1)
CPSE Rd,Rr Compare, skip if Equal if (Rd = Rr) PC PC + 2 or 3 None 1 / 2 / 3 1 / 2 / 3 1 / 2 / 3 1 / 2
CP Rd,Rr Compare Rd - Rr     Z,C,N,V,S,H 1 1 1 1
CPC Rd,Rr Compare with Carry Rd - Rr - C     Z,C,N,V,S,H 1 1 1 1
CPI Rd,K Compare with Immediate Rd - K     Z,C,N,V,S,H 1 1 1 1
SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b) = 0) PC PC + 2 or 3 None 1 / 2 / 3 1 / 2 / 3 1 / 2 / 3 1 / 2
SBRS Rr, b Skip if Bit in Register Set if (Rr(b) = 1) PC PC + 2 or 3 None 1 / 2 / 3 1 / 2 / 3 1 / 2 / 3 1 / 2
SBIC A, b Skip if Bit in I/O Register Cleared if (I/O(A,b) = 0) PC PC + 2 or 3 None 1 / 2 / 3 2 / 3 / 4 1 / 2 / 3 1 / 2
SBIS A, b Skip if Bit in I/O Register Set If (I/O(A,b) =1) PC PC + 2 or 3 None 1 / 2 / 3 2 / 3 / 4 1 / 2 / 3 1 / 2
BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BREQ k Branch if Equal if (Z = 1) then PC PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BRNE k Branch if Not Equal if (Z = 0) then PC PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BRCS k Branch if Carry Set if (C = 1) then PC PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BRCC k Branch if Carry Cleared if (C = 0) then PC PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BRSH k Branch if Same or Higher if (C = 0) then PC PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BRLO k Branch if Lower if (C = 1) then PC PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BRMI k Branch if Minus if (N = 1) then PC PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BRPL k Branch if Plus if (N = 0) then PC PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BRLT k Branch if Less Than, Signed if (N ⊕ V= 1) then PC PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BRHS k Branch if Half Carry Flag Set if (H = 1) then PC PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BRTS k Branch if T Flag Set if (T = 1) then PC PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BRTC k Branch if T Flag Cleared if (T = 0) then PC PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BRVS k Branch if Overflow Flag is Set if (V = 1) then PC PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BRIE k Branch if Interrupt Enabled if (I = 1) then PC PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
BRID k Branch if Interrupt Disabled if (I = 0) then PC PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2
Table 4. Data Transfer Instructions
Mnemonic Operands Description   Op   Flags #Clocks AVR #Clocks AVRxm #Clocks AVRxt #Clocks AVRrc
MOV Rd, Rr Copy Register Rd Rr None 1 1 1 1
MOVW Rd, Rr Copy Register Pair Rd+1:Rd Rr+1:Rr None 1 1 1 N/A
LDI Rd, K Load Immediate Rd K None 1 1 1 1
LDS Rd, k Load Direct from data space Rd (k) None 2(1) 2(1) 3(1) 2
LD Rd, X Load Indirect Rd (X) None 2(1) 1(1) 2(1) 1 / 2
LD Rd, X+ Load Indirect and Post-Increment

Rd

X

←


(X)


X + 1

None 2(1) 1(1) 2(1) 2 / 3
LD Rd, -X Load Indirect and Pre-Decrement

X

Rd

←


X - 1


(X)

None 2(1) 2(1) 2(1) 2 / 3
LD Rd, Y Load Indirect Rd (Y) None 2(1) 1(1) 2(1) 1 / 2
LD Rd, Y+ Load Indirect and Post-Increment

Rd

Y

←


(Y)

Y + 1

None 2(1) 1(1) 2(1) 2 / 3
LD Rd, -Y Load Indirect and Pre-Decrement

Y

Rd

←


Y - 1


(Y)

None 2(1) 2(1) 2(1) 2 / 3
LDD Rd, Y+q Load Indirect with Displacement Rd (Y + q) None 2(1) 2(1) 2(1) N/A
LD Rd, Z Load Indirect Rd (Z) None 2(1) 1(1) 2(1) 1 / 2
LD Rd, Z+ Load Indirect and Post-Increment

Rd

Z

←


(Z)

Z+1

None 2(1) 1(1) 2(1) 2 / 3
LD Rd, -Z Load Indirect and Pre-Decrement

Z

Rd

←


Z - 1

(Z)

None 2(1) 2(1) 2(1) 2 / 3
LDD Rd, Z+q Load Indirect with Displacement Rd (Z + q) None 2(1) 2(1) 2(1) N/A
STS k, Rr Store Direct to Data Space (k) Rd None 2(1)(2) 2(1)(2) 2(1)(2) 1
ST X, Rr Store Indirect (X) Rr None 1(1)(2) 1(1)(2) 1(1)(2) 1
ST X+, Rr Store Indirect and Post-Increment

(X)

X

←


Rr

X + 1

None 1(1)(2) 1(1)(2) 1(1)(2) 1
ST -X, Rr Store Indirect and Pre-Decrement

X

(X)

←


X - 1


Rr

None 2(1)(2) 2(1)(2) 1(1)(2) 2
ST Y, Rr Store Indirect (Y) Rr None 2(1)(2) 1(1)(2) 1(1)(2) 1
ST Y+, Rr Store Indirect and Post-Increment

(Y)

Y

←


Rr

Y + 1

None 2(1)(2) 1(1)(2) 1(1)(2) 1
ST -Y, Rr Store Indirect and Pre-Decrement

Y

(Y)

←


Y - 1

Rr

None 2(1)(2) 2(1)(2) 1(1)(2) 2
STD Y+q, Rr Store Indirect with Displacement (Y + q) Rr None 2(1)(2) 2(1)(2) 1(1)(2) N/A
ST Z, Rr Store Indirect (Z) Rr None 2(1)(2) 1(1)(2) 1(1)(2) 1
ST Z+, Rr Store Indirect and Post-Increment

(Z)

Z

←


Rr


Z + 1
None 2(1)(2) 1(1)(2) 1(1)(2) 1
ST -Z, Rr Store Indirect and Pre-Decrement Z Z - 1 None 2(1)(2) 2(1)(2) 1(1)(2) 2
STD Z+q,Rr Store Indirect with Displacement (Z + q) Rr None 2(1)(2) 2(1)(2) 1(1)(2) N/A
LPM   Load Program Memory R0 (Z) None 3 3 3 N/A
LPM Rd, Z Load Program Memory Rd (Z) None 3 3 3 N/A
LPM Rd, Z+ Load Program Memory and Post-Increment

Rd

Z

←


(Z)

Z + 1

None 3 3 3 N/A
ELPM   Extended Load Program Memory R0 (RAMPZ:Z) None 3 3 3 N/A
ELPM Rd, Z Extended Load Program Memory Rd (RAMPZ:Z) None 3 3 3 N/A
ELPM Rd, Z+ Extended Load Program Memory and Post-Increment

Rd

(RAMPZ:Z)

←


(RAMPZ:Z)

(RAMPZ:Z) + 1

None 3 3 3 N/A
SPM   Store Program Memory (RAMPZ:Z) R1:R0 None (4) (4) 4(3) N/A
SPM Z+ Store Program Memory and Post- Increment by 2

(RAMPZ:Z)

Z

←


R1:R0

Z + 2

None (4) (4) 4(3) N/A
IN Rd, A In From I/O Location Rd I/O(A) None 1 1 1 1
OUT A, Rr Out To I/O Location I/O(A) Rr None 1 1 1 1
PUSH Rr Push Register on Stack STACK Rr None 2 1(1) 1 1(1)
POP Rd Pop Register from Stack Rd STACK None 2 2(1) 2 3(1)
XCH Z, Rd Exchange

(Z)

Rd

←


Rd

(Z)

None N/A 1 N/A N/A
LAS Z, Rd Load and Set

(Z)

Rd

←


Rd v (Z)

(Z)

None N/A 1 N/A N/A
LAC Z, Rd Load and Clear

(Z)

Rd

←


($FF – Rd) • (Z)

(Z)

None N/A 1 N/A N/A
LAT Z, Rd Load and Toggle

(Z)

Rd

←


Rd ⊕ (Z)

(Z)

None N/A 1 N/A N/A
Table 5. Bit and Bit-test Instructions
Mnemonic Operands Description   Op   Flags #Clocks AVR #Clocks AVRxm #Clocks AVRxt #Clocks AVRrc
LSL Rd Logical Shift Left

Rd(n+1)

Rd(0)

C

Rd(n)


0

Rd(7)

Z,C,N,V,H 1 1 1 1
LSR Rd Logical Shift Right

Rd(n)

Rd(7)

C

Rd(n+1)


0

Rd(0)

Z,C,N,V 1 1 1 1
ROL Rd Rotate Left Through Carry

Rd(0)

Rd(n+1)

C

C

Rd(n)

Rd(7)

Z,C,N,V,H 1 1 1 1
ROR Rd Rotate Right Through Carry

Rd(7)

Rd(n)

C

C

Rd(n+1)

Rd(0)

Z,C,N,V 1 1 1 1
ASR Rd Arithmetic Shift Right Rd(n) Rd(n+1), n=0..6 Z,C,N,V 1 1 1 1
SWAP Rd Swap Nibbles Rd(3..0) Rd(7..4) None 1 1 1 1
SBI A, b Set Bit in I/O Register I/O(A, b) 1 None 2 1 1 1
CBI A, b Clear Bit in I/O Register I/O(A, b) 0 None 2 1 1 1
BST Rr, b Bit Store from Register to T T Rr(b) T 1 1 1 1
BLD Rd, b Bit load from T to Register Rd(b) T None 1 1 1 1
BSET s Flag Set SREG(s) 1 SREG(s) 1 1 1 1
BCLR s Flag Clear SREG(s) 0 SREG(s) 1 1 1 1
SEC   Set Carry C 1 C 1 1 1 1
CLC   Clear Carry C 0 C 1 1 1 1
SEN   Set Negative Flag N 1 N 1 1 1 1
CLN   Clear Negative Flag N 0 N 1 1 1 1
SEZ   Set Zero Flag Z 1 Z 1 1 1 1
CLZ   Clear Zero Flag Z 0 Z 1 1 1 1
SEI   Global Interrupt Enable I 1 I 1 1 1 1
CLI   Global Interrupt Disable I 0 I 1 1 1 1
SES   Set Signed Test Flag S 1 S 1 1 1 1
CLS   Clear Signed Test Flag S 0 S 1 1 1 1
SEV   Set Two’s Complement Overflow V 1 V 1 1 1 1
CLV   Clear Two’s Complement Overflow V 0 V 1 1 1 1
SET   Set T in SREG T 1 T 1 1 1 1
CLT   Clear T in SREG T 0 T 1 1 1 1
SEH   Set Half Carry Flag in SREG H 1 H 1 1 1 1
CLH   Clear Half Carry Flag in SREG H 0 H 1 1 1 1
Table 6. MCU Control Instructions
Mnemonic Operands Description Operation Flags #Clocks AVR #Clocks AVRxm #Clocks AVRxt #Clocks AVRrc
BREAK   Break (See also in Debug interface description) None 1 1 1 1
NOP   No Operation   None 1 1 1 1
SLEEP   Sleep (see also power management and sleep description) None 1 1 1 1
WDR   Watchdog Reset (see also Watchdog Controller description) None 1 1 1 1
Note:
  1. Cycle time for data memory accesses assume internal RAM access, and are not valid for accesses through the NVM controller. A minimum of one extra cycle must be added when accessing memory through the NVM controller (such as Flash and EEPROM), but depending on simultaneous accesses by other masters or the NVM controller state, there may be more than one extra cycle.
  2. One extra cycle must be added when accessing lower (64 bytes of) I/O space.
  3. The instruction is not available on all devices.
  4. Device dependent. See the device specific datasheet.