Description

Loads one byte indirect with or without displacement from the data space to a register. For parts with SRAM, the data space consists of the Register File, I/O memory, and internal SRAM (and external SRAM if applicable). For parts without SRAM, the data space consists of the Register File only. In some parts the Flash Memory has been mapped to the data space and can be read using this command. The EEPROM has a separate address space.

The data location is pointed to by the Y (16 bits) Pointer Register in the Register File. Memory access is limited to the current data segment of 64KB. To access another data segment in devices with more than 64KB data space, the RAMPY in register in the I/O area has to be changed.

The Y-pointer Register can either be left unchanged by the operation, or it can be post-incremented or pre-decremented. These features are especially suited for accessing arrays, tables, and Stack Pointer usage of the Y-pointer Register. Note that only the low byte of the Y-pointer is updated in devices with no more than 256 bytes data space. For such devices, the high byte of the pointer is not used by this instruction and can be used for other purposes. The RAMPY Register in the I/O area is updated in parts with more than 64KB data space or more than 64KB Program memory, and the increment/decrement/displacement is added to the entire 24-bit address on such devices.

Not all variants of this instruction is available in all devices. Refer to the device specific instruction set summary.

In the Reduced Core tinyAVR the LD instruction can be used to achieve the same operation as LPM since the program memory is mapped to the data memory space.

The result of these combinations is undefined:

LD r28, Y+

LD r29, Y+

LD r28, -Y

LD r29, -Y

Using the Y-pointer:

Operation:

Comment:

(i)

Rd ← (Y)

Y: Unchanged

(ii)

Rd ← (Y), Y ← Y + 1

Y: Post incremented

(iii)

Y ← Y - 1, Rd ← (Y)

Y: Pre decremented

(iv)

Rd ← (Y+q)

Y: Unchanged, q: Displacement

Syntax:

Operands:

Program Counter:

(i)

LD Rd, Y

0 ≤ d ≤ 31

PC ← PC + 1

(ii)

LD Rd, Y+

0 ≤ d ≤ 31

PC ← PC + 1

(iii)

LD Rd, -Y

0 ≤ d ≤ 31

PC ← PC + 1

(iv)

LDD Rd, Y+q

0 ≤ d ≤ 31, 0 ≤ q ≤ 63

PC ← PC + 1

16-bit Opcode:

(i) 1000 000d dddd 1000
(ii) 1001 000d dddd 1001
(iii) 1001 000d dddd 1010
(iv) 10q0 qq0d dddd 1qqq