Status
Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PWMACTB | PWMACTA | CMDRDY | ENRDY | ||||
AccessR/W | R/W | R | R | ||||
Reset0 | 0 | 0 | 0 |
Command Ready
This status bit tells when a command is synced to the TCD domain and the system is ready to receive new commands.
Enable Ready
This status bit tells when the ENABLE value in TCDn.CTRLA is synced to the TCD domain and is ready to be written to again.
PWM Activity on x
This bit is set by hardware each time the output WO toggles from 0 to 1 or from 1 to 0.
This status bit must be cleared by software by writing a '1' to it before new PWM activity can be detected.