WDTCSR – Watchdog Timer Control Register

0x60 [ID-000004d0]

Bit 7 – WDIF: Watchdog Interrupt Flag

Watchdog Interrupt Flag

This bit is set when a time out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, WDIF is cleared by writing a '1' to it. When the I-bit in SREG and WDIE are set, the Watchdog Timeout Interrupt is executed.

Bit 6 – WDIE: Watchdog Interrupt Enable

Watchdog Interrupt Enable

When this bit is written to '1' and the I-bit in the Status register is set, the Watchdog Interrupt is enabled. If WDE is cleared in combination with this setting, the Watchdog Timer is in Interrupt mode, and the corresponding interrupt is executed if timeout in the Watchdog Timer occurs. If WDE is set, the Watchdog Timer is in Interrupt and System Reset mode. The first timeout in the Watchdog Timer will set WDIF. Executing the corresponding interrupt vector will clear WDIE and WDIF automatically by hardware (the Watchdog goes to System Reset mode).

This is useful for keeping the Watchdog Timer security while using the interrupt. To stay in Interrupt and System Reset mode, WDIE must be set after each interrupt. This should not be done within the interrupt service routine itself, as this might compromise the safety function of the Watchdog System Reset mode. If the interrupt is not executed before the next timeout, a System Reset will be applied.

Table 1. Watchdog Timer Configuration
WDTON(1) WDE WDIE Mode Action on Time-out
1 0 0 Stopped None
1 0 1 Interrupt mode Interrupt
1 1 0 System Reset mode Reset
1 1 1 Interrupt and System Reset mode Interrupt, then go to System Reset mode
0 x x System Reset mode Reset
Note: 1. WDTON Fuse set to '0' means programmed and '1' means unprogrammed.

Bit 5 – WDP[3]: Watchdog Timer Prescaler 3

Watchdog Timer Prescaler 3

Bit 4 – WDCE: Watchdog Change Enable

Watchdog Change Enable

This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit, and/or change the prescaler bits, WDCE must be set. Once written to '1', hardware will clear WDCE after four clock cycles. Refer to Overview in section Watchdog Timer for information on how to use WDCE.

Bit 3 – WDE: Watchdog System Reset Enable

Watchdog System Reset Enable

WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets during conditions causing failure, and a safe start-up after the failure.

Bits 2:0 – WDP[2:0]: Watchdog Timer Prescaler 2, 1, and 0

Watchdog Timer Prescaler 2, 1, and 0

The WDP[3:0] bits determine the Watchdog Timer prescaling when the Watchdog Timer is running. The different prescaling values and their corresponding time out periods are shown in the following table.

Table 2. Watchdog Timer Prescale Select
WDP[3] WDP[2] WDP[1] WDP[0] Number of WDT Oscillator (Cycles) Oscillator
0 0 0 0 2K (2048) 16 ms
0 0 0 1 4K (4096) 32 ms
0 0 1 0 8K (8192) 64 ms
0 0 1 1 16K (16384) 0.125s
0 1 0 0 32K (32768) 0.25s
0 1 0 1 64K (65536) 0.5s
0 1 1 0 128K (131072) 1.0s
0 1 1 1 256K (262144) 2.0s
1 0 0 0 512K (524288) 4.0s
1 0 0 1 1024K (1048576) 8.0s
1 0 1 0 Reserved
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1