TWI Control Register n

The TWCRn is used to control the operation of the TWI n. It is used to enable the TWI n, to initiate a Master access by applying a START condition to the bus, to generate a Receiver acknowledge, to generate a stop condition, and to control halting of the bus while the data to be written to the bus are written to the TWDRn. It also indicates a write collision if data is attempted written to TWDRn while the register is inaccessible.
0xBC + n*0x20 [n=0..1]

Bit 7 – TWINT: TWI Interrupt Flag

TWI Interrupt Flag

This bit is set by hardware when the TWI n has finished its current job and expects application software response. If the I-bit in the Status Register (SREG.I) and the TWI Interrupt Enable bit in the TWI Control Register n (TWCRn.TWIE) are set, the MCU will jump to the TWI Interrupt Vector. While the TWINT Flag is set, the SCL low period is stretched. The TWINT Flag must be cleared by software by writing a logic one to it.

Note that this flag is not automatically cleared by hardware when executing the interrupt routine. Also note that clearing this flag starts the operation of the TWI n, so all accesses to the TWI Address Register (TWARn), TWI Status Register (TWSRn), and TWI Data Register (TWDRn) must be complete before clearing this flag.

Bit 6 – TWEA: TWI Enable Acknowledge

TWI Enable Acknowledge

This bit controls the generation of the acknowledge pulse. If the TWEA bit is written to one, the ACK pulse is generated on the TWI n bus if the following conditions are met:

  1. 1.The device’s own slave address has been received.
  2. 2.A general call has been received, while the TWGCE bit in the TWARn is set.
  3. 3.A data byte has been received in Master Receiver or Slave Receiver mode.

By writing the TWEA bit to zero, the device can be virtually disconnected from the two-wire Serial Bus temporarily. Address recognition can then be resumed by writing the TWEA bit to one again.

Bit 5 – TWSTA: TWI START Condition

TWI START Condition

The application writes the TWSTA bit to one when it desires TWI n to become a Master on the two-wire Serial Bus. The TWI n hardware checks if the bus is available, and generates a START condition on the bus if it is free. However, if the bus is not free, the TWI n waits until a STOP condition is detected, and then generates a new START condition to claim the bus Master status. TWSTA must be cleared by software when the START condition has been transmitted.

Bit 4 – TWSTO: TWI STOP Condition

TWI STOP Condition

Writing the TWSTO bit to one in Master mode will generate a STOP condition on the two-wire Serial Bus TWI n. When the STOP condition is executed on the bus, the TWSTO bit is automatically cleared. In Slave mode, setting the TWSTO bit can be used to recover from an error condition. This will not generate a STOP condition, but the TWI n returns to a well-defined unaddressed Slave mode and releases the SCL and SDA lines to a high impedance state.

Bit 3 – TWWC: TWI Write Collision Flag

TWI Write Collision Flag

The TWWC bit is set when attempting to write to the TWI n Data Register (TWDRn) when TWCRn.TWINT is low. This flag is cleared by writing the TWDRn register when TWINT is high.

Bit 2 – TWEN: TWI Enable

TWI Enable

The TWEN bit enables TWI n operation and activates the TWI n interface. When TWEN is written to one, the TWI n takes control over the I/O pins connected to the SCL and SDA pins, enabling the slew-rate limiters and spike filters. If this bit is written to zero, the TWI n is switched OFF and all transmissions of TWI n are terminated, regardless of any ongoing operation.

Bit 0 – TWIE: TWI Interrupt Enable

TWI Interrupt Enable

When this bit is written to one, and the I-bit in the Status Register (SREG.I) is set, the TWI n interrupt request will be activated for as long as the TWCRn.TWINT Flag is high.