When addressing I/O registers as data space using LD
and ST instructions, the provided offset must be used. When using the I/O specific
commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset
within 0x00 - 0x3F.
The device is a complex microcontroller with more peripheral units than can be
supported within the 64 locations reserved in Opcode for the IN and OUT
instructions. For the extended I/O space from 0x60 in SRAM, only the ST/STS/STD and
LD/LDS/LDD instructions can be used.
Analog Comparator
Disable
When this bit is
written logic one, the power to the analog comparator is switched off. This bit can
be set at any time to turn off the analog comparator. This will reduce power
consumption in Active and Idle mode. When changing the ACD bit, the analog
comparator interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise,
an interrupt can occur when the bit is changed.
Analog Comparator Bandgap Select
When this bit is
set, a fixed bandgap reference voltage replaces the positive input to the analog
comparator. When this bit is cleared, AIN0 is applied to the positive input of the
analog comparator. When the bandgap reference is used as input to the analog
comparator, it will take a certain time for the voltage to stabilize. If not
stabilized, the first conversion may give a wrong value.
Analog Comparator Output
The output of the
analog comparator is synchronized and then directly connected to ACO. The
synchronization introduces a delay of 1 - 2 clock cycles.
Analog Comparator Interrupt Flag
This bit is set by
hardware when a comparator output event triggers the interrupt mode defined by ACIS1
and ACIS0. The analog comparator interrupt routine is executed if the ACIE bit is
set and the I-bit in SREG is set. ACI is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a
logic one to the flag.
Analog Comparator Interrupt Enable
When the ACIE bit is
written logic one and the I-bit in the status register is set, the analog comparator
interrupt is activated. When written logic zero, the interrupt is
disabled.
Analog Comparator Input Capture Enable
When written logic
one, this bit enables the input capture function in Timer/Counter1 to be triggered
by the analog comparator. The comparator output is in this case directly connected
to the input capture front-end logic, making the comparator utilize the noise
canceler and edge select features of the Timer/Counter1 input capture interrupt.
When written logic zero, no connection between the analog comparator and the input
capture function exists. To make the comparator trigger the Timer/Counter1 input
capture interrupt, the ICIE1 bit in the Timer Interrupt Mask Register (TIMSK1) must
be set.
Analog Comparator
Interrupt Mode Select
These bits determine which comparator events that trigger the analog
comparator interrupt.
Table 1. ACIS[1:0] Settings
ACIS1 |
ACIS0 |
Interrupt Mode |
0 |
0 |
Comparator interrupt on output toggle. |
0 |
1 |
Reserved |
1 |
0 |
Comparator interrupt on falling output
edge. |
1 |
1 |
Comparator interrupt on rising output
edge. |
When changing the ACIS1/ACIS0 bits, the analog comparator Interrupt
must be disabled by clearing its interrupt enable bit in the ACSR register.
Otherwise, an interrupt can occur when the bits are changed.