Counter Unit

The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit, as shown in the block diagram:

Figure 1. Counter Unit Block Diagram
Note: The ā€œnā€ in the register and bit names indicates the device number (n = 1, 3, 4 for Timer/Counter 1, 3, 4), and the ā€œxā€ indicates Output Compare unit (A/B).
Table 1. Signal Description (Internal Signals)
Signal Name Description
Count Increment or decrement TCNTn by 1.
Direction Select between increment and decrement.
Clear Clear TCNTn (set all bits to zero).
clkTn Timer/Counter clock.
TOP Signalize that TCNTn has reached maximum value.
BOTTOM Signalize that TCNTn has reached minimum value (zero).
The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNTnH) containing the upper eight bits of the counter, and Counter Low (TCNTnL) containing the lower eight bits. The TCNTnH register can only be accessed indirectly by the CPU. When the CPU does an access to the TCNTnH I/O location, the CPU accesses the high byte temporary register (TEMP). The temporary register is updated with the TCNTnH value when the TCNTnL is read, and TCNTnH is updated with the temporary register value when TCNTnL is written. This allows the CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus.
Note: That there are special cases when writing to the TCNTn register while the counter is counting will give unpredictable results. These special cases are described in the sections where they are of importance.

Depending on the selected mode of operation, the counter is cleared, incremented, or decremented at each timer clock (clkTn). The clock clkTn can be generated from an external or internal clock source, as selected by the clock select bits in the Timer/Countern control register B (TCCRnB.CS[2:0]). When no clock source is selected (CS[2:0]=0x0) the timer is stopped. However, the TCNTn value can be accessed by the CPU, independent of whether clkTn is present or not. A CPU write overrides (i.e., has priority over) all counter clear or count operations.

The counting sequence is determined by the setting of the waveform generation mode bits in the Timer/Counter Control Registers A and B (TCCRnB.WGMn[3:2] and TCCRnA.WGMn[1:0]). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare outputs OC0x. For more details about advanced counting sequences and waveform generation, see Modes of Operation.

The Timer/Counter Overflow Flag in the TCn Interrupt Flag Register (TIFRn.TOV) is set according to the mode of operation selected by the WGMn[3:0] bits. TOV can be used for generating a CPU interrupt.