Block Diagram

In the USART block diagram, the CPU accessible I/O registers and I/O pins are shown in bold. The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock generator, transmitter, and receiver. Control registers are shared by all units. The clock generation logic consists of synchronization logic for external clock input used by synchronous slave operation, and the baud rate generator. The XCKn (Transfer clock) pin is only used by synchronous transfer mode. The transmitter consists of a single write buffer, a serial Shift register, parity generator, and control logic for handling different serial frame formats. The write buffer allows a continuous transfer of data without any delay between frames. The receiver is the most complex part of the USART module due to its clock and data recovery units. The recovery units are used for asynchronous data reception. In addition to the recovery units, the receiver includes a parity checker, control logic, a Shift register, and a two-level receive buffer (UDRn). The receiver supports the same frame formats as the transmitter and can detect frame error, data overrun, and parity errors.

Figure 1. USART Block Diagram
Note: Refer to the Pin Configurations and the I/O-Ports description for USART pin placement.