Sleep Mode Control Register

The Sleep Mode Control Register contains control bits for power management.

When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.

The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in Opcode for the IN and OUT instructions. For the extended I/O space from 0x60 in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

When addressing as I/O Register: address offset is 0x33

Bits 3:1 – SM[2:0]: Sleep Mode Select

Sleep Mode Select

The SM[2:0] bits select between the five available sleep modes.

Table 1. Sleep Mode Select
SM[2:0] Sleep Mode
000 Idle
001 ADC Noise Reduction
010 Power-down
011 Power-save
100 Reserved
101 Reserved
110 Standby(1)
111 Extended Standby(1)
  1. 1.Standby mode is only recommended for use with external crystals or resonators.

Bit 0 – SE: Sleep Enable

Sleep Enable

The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up.