Clock Generation

The clock generation logic generates the base clock for the transmitter and receiver. The USART supports four modes of clock operation: Normal asynchronous, Double Speed asynchronous, Master synchronous, and Slave synchronous mode. The USART mode select bit 0 in the USART Control and Status Register n C (UCSRnC.UMSELn0) selects between asynchronous and synchronous operation. Double speed (asynchronous mode only) is controlled by the U2Xn found in the UCSRnA register. When using synchronous mode (UMSELn0=1), the data direction register for the XCKn pin (DDR_XCKn) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCKn pin is only active when using Synchronous mode.

Below is a block diagram of the clock generation logic.

Figure 1. Clock Generation Logic, Block Diagram

Signal description: