TC4 Control Register B
| Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ICNC4 | ICES4 | WGM4[3] | WGM4[2] | CS4[2:0] | |||
| AccessR/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Input Capture Noise Canceler
Writing this bit to '1' activates the Input Capture Noise Canceler. When the noise canceler is activated, the input from the Input Capture pin (ICP4) is filtered. The filter function requires four successive equal valued samples of the ICP4 pin for changing its output. The Input Capture is therefore delayed by four Oscillator cycles when the noise canceler is enabled.
Input Capture Edge Select
This bit selects which edge on the Input Capture pin (ICP4) that is used to trigger a capture event. When the ICES4 bit is written to zero, a falling (negative) edge is used as a trigger, and when the ICES4 bit is written to '1', a rising (positive) edge will trigger the capture.
When a capture is triggered according to the ICES4 setting, the counter value is copied into the Input Capture Register (ICR4). The event will also set the Input Capture Flag (ICF4), and this can be used to cause an Input Capture Interrupt if this interrupt is enabled.
When the ICR4 is used as TOP value (see description of the WGM4[3:0] bits located in the TCCR4A and the TCCR4B Register), the ICP4 is disconnected and consequently, the Input Capture function is disabled.
Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter. Refer to Figure 1 and Figure 2.
| CS4[2] | CS4[1] | CS4[0] | Description |
|---|---|---|---|
| 0 | 0 | 0 | No clock source (Timer/Counter stopped). |
| 0 | 0 | 1 | clkI/O/1 (No prescaling) |
| 0 | 1 | 0 | clkI/O/8 (From prescaler) |
| 0 | 1 | 1 | clkI/O/64 (From prescaler) |
| 1 | 0 | 0 | clkI/O/256 (From prescaler) |
| 1 | 0 | 1 | clkI/O/1024 (From prescaler) |
| 1 | 1 | 0 | External clock source on Tn pin. Clock on falling edge. |
| 1 | 1 | 1 | External clock source on Tn pin. Clock on rising edge. |
Waveform Generation Mode