Enable External Clock Input
When EXCLK is
written to one, and asynchronous clock is selected, the external clock input buffer
is enabled and an external clock can be input on Timer Oscillator 1 (TOSC1) pin
instead of a 32 kHz crystal. Writing to EXCLK should be done before asynchronous
operation is selected. Note that the crystal oscillator will run only when this bit
is zero.
Asynchronous Timer/Counter2
When AS2 is written
to zero, Timer/Counter2 is clocked from the I/O clock, clkI/O. When AS2 is written
to one, Timer/Counter2 is clocked from a crystal oscillator connected to the Timer
Oscillator 1 (TOSC1) pin. When the value of AS2 is changed, the contents of TCNT2,
OCR2A, OCR2B, TCCR2A, and TCCR2B might be corrupted.
Timer/Counter2 Update Busy
When Timer/Counter2 operates asynchronously and TCNT2 is written,
this bit becomes set. When TCNT2 has been updated from the temporary storage
register, this bit is cleared by hardware. A logical zero in this bit indicates that
TCNT2 is ready to be updated with a new value.
Output Compare
Register2A Update Busy
When Timer/Counter2 operates asynchronously and OCR2A is written,
this bit becomes set. When OCR2A has been updated from the temporary storage
register, this bit is cleared by hardware. A logical zero in this bit indicates that
OCR2A is ready to be updated with a new value.
Output Compare
Register2B Update Busy
When Timer/Counter2 operates asynchronously and OCR2B is written,
this bit becomes set. When OCR2B has been updated from the temporary storage
register, this bit is cleared by hardware. A logical zero in this bit indicates that
OCR2B is ready to be updated with a new value.
Timer/Counter Control Register2 Update
Busy
When Timer/Counter2 operates asynchronously and TCCR2A is written,
this bit becomes set. When TCCR2A has been updated from the temporary storage
register, this bit is cleared by hardware. A logical zero in this bit indicates that
TCCR2A is ready to be updated with a new value.
Timer/Counter Control Register2 Update
Busy
When Timer/Counter2 operates asynchronously and TCCR2B is written, this bit
becomes set. When TCCR2B has been updated from the temporary storage register,
this bit is cleared by hardware. A logical zero in this bit indicates that
TCCR2B is ready to be updated with a new value.
If a write is performed to any of the five Timer/Counter2 Registers
while its Update Busy flag is set, the updated value might get corrupted and
cause an unintentional interrupt to occur.