ADC Functionality Cannot be Ensured with CLKADC Above 1.5 MHz and a Setting of 25% Duty Cycle

The ADC functionality cannot be ensured if CLKADC > 1.5 MHz with ADCn.CALIB.DUTYCYC set to ‘1’.

Work around

If ADC is operated with CLKADC > 1.5 MHz, ADCn.CALIB.DUTYCYC must be set to ‘0’ (50% duty cycle).

Affected Silicon Revisions

ATtiny416
Rev. A Rev. B            
X X            
ATtiny816
Rev. A Rev. B            
X X            
Parent topic: ADC - Analog-to-Digital Converter