If TWI is enabled in Master mode followed by an immediate write to the MADDR register the bus monitor recognizes the Start bit as a Stop bit.
Wait for a minimum of two clock cycles from TWI.MCTRLA.ENABLE until TWI.MADDR is written.
ATtiny416 | |||||||
---|---|---|---|---|---|---|---|
Rev. A | Rev. B | ||||||
X | - | ||||||
ATtiny816 | |||||||
Rev. A | Rev. B | ||||||
X | X |