External Interrupt Mask Register
Name:
EIMSK
Offset:
0x13
Reset:
0x00
Access:
-
Bit76543210
INT0
AccessR/W
Reset0

Bit 0 – INT0: External Interrupt Request 0 Enable

External Interrupt Request 0 Enable

When the INT0 bit is set ('1') and the I-bit in the Status Register (SREG) is set ('1'), the external pin interrupt is enabled. The Interrupt Sense Control 0 bits in the External Interrupt Control Register A (EICRA.ISC0) define whether the external interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from the INT0 Interrupt Vector.