Clock Generation

The Clock Generation logic generates the base clock for the Transmitter and Receiver. The USART supports four modes of clock operation: Normal asynchronous, Double Speed asynchronous, Master synchronous and Slave synchronous mode. The USART Mode Select bit 0 in the USART Control and Status Register n C (UCSRnC.UMSELn0) selects between asynchronous and synchronous operation. Double Speed (asynchronous mode only) is controlled by the U2X0 found in the UCSRnA Register. When using synchronous mode (UMSELn0=1), the Data Direction Register for the XCKn pin (DDR_XCKn) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCKn pin is only active when using synchronous mode.

Below is a block diagram of the clock generation logic.

Figure 1. Clock Generation Logic, Block Diagram

Signal description:

txclk: Transmitter clock (internal signal).
rxclk: Receiver base clock (internal signal).
xcki: Input from XCKn pin (internal signal). Used for synchronous slave operation.
xcko: Clock output to XCKn pin (internal signal). Used for synchronous master operation.
f_osc: System clock frequency.