Alternate Functions of Port A

The Port A pins with alternate functions are shown in the table below:

Table 1. Port A Pins Alternate Functions
Port Pin Alternate Functions
PA[0]

ADC0: ADC Input Channel 0

AIN0: Analog Comparator, Positive Input

T0: Timer/Counter0 Clock Source (default location)

PCINT0: Pin Change Interrupt source 0

CLKI: External Clock

TPICLK: Serial Programming Clock

PA[1]

ADC1: ADC Input Channel 1

AIN1: Analog Comparator, Negative Input

OC0B: Timer/Counter0 Compare Match B Output (default
    location)

PCINT1: Pin Change Interrupt source 1

TPIDATA: Serial Programming Data

PA[2]

PCINT2: Pin Change Interrupt source 2

RESET: Reset Pin

PA[3]

OC0A: Timer/Counter0 Compare Match A Output (alternative
    location)

PCINT3: Pin Change Interrupt source 3

PA[4]

ICP0: Timer/Counter0 Input Capture Input (alternative
    location)

PCINT4: Pin Change Interrupt source 4

PA[5]

ADC2: ADC Input Channel 2

OC0B: Timer/Counter0 Compare Match B Output (alternative
    location)

PCINT5: Pin Change Interrupt source 5

PA[6]

ADC3: ADC Input Channel 3

PCINT6: Pin Change Interrupt source 6

PA[7]

PCINT7: Pin Change Interrupt source 7

The alternate pin configuration is as follows:

The following tables relate the alternate functions of Port B to the overriding signals shown in the figure of Alternate Port Functions.

Table 2. Overriding Signals for Alternate Functions in PA[7:6]
Signal 
Name PA7/PCINT7 PA6/ADC3/PCINT6
PUOE 0 0
PUOV 0 0
DDOE 0 0
DDOV 0 0
PVOE 0 0
PVOV 0 0
PTOE 0 0
DIEOE (PCINT7 • PCIE0) (PCINT6 • PCIE0) + ADC3D
DIEOV PCINT7 • PCIE0 PCINT6 • PCIE0
DI PCINT7 Input PCINT6 input
AIO - ADC3
Table 3. Overriding Signals for Alternate Functions in PA[5:4]
Signal 
Name PA5/ADC2/OC0B/PCINT5 PA4/ICP0/PCINT4
PUOE 0 0
PUOV 0 0
DDOE 0 0
DDOV 0 0
PVOE (OC0B Enable • REMAP) 0
PVOV (OC0B • REMAP) 0
PTOE 0 0
DIEOE (PCINT5 • PCIE0) + ADC2D (PCINT4 • PCIE0)
DIEOV PCINT5 • PCIE0 (PCINT4 • PCIE0)
DI PCINT5 Input ICP0/PCINT4 Input
AIO ADC2 -
Table 4. Overriding Signals for Alternate Functions in PA[3:2]
Signal 
Name PA3/OC0A/PCINT3 PA4/ICP0/PCINT4
PUOE 0 RSTDISBL(1)
PUOV 0 1
DDOE 0 RSTDISBL(1)
DDOV 0 0
PVOE (OC0A Enable • REMAP) 0
PVOV (OC0A • REMAP) 0
PTOE 0 0
DIEOE (PCINT3 • PCIE0) RSTDISBL(1) + (PCINT2 • PCIE0)
DIEOV PCINT3 • PCIE0 RSTDISBL • PCINT2 • PCIE0
DI PCINT3 Input PCINT2 input
AIO - -
Note:
  1. RSTDISBL is 1 when the configuration bit is “0” (Programmed).
Table 5. Overriding Signals for Alternate Functions in PA[1:0]
Signal 
Name PA1/ADC1/AIN1/OC0B/PCINT1 PA0/ADC0/AIN0/CLKI/T0/PCINT0
PUOE 0 EXT_CLOCK(1)
PUOV 0 0
DDOE 0 EXT_CLOCK(1)
DDOV 0 0
PVOE (OC0B Enable • REMAP) EXT_CLOCK(1)
PVOV (OC0B • REMAP) 0
PTOE 0 0
DIEOE (PCINT1 • PCIE0) + ADC1D EXT_CLOCK(1) + (PCINT0 • PCIE0) + ADC0D
DIEOV PCINT1 • PCIE0 EXT_CLOCK(1)PWR_DOWN) + (EXT_CLOCK(1)• PCINT0 • PCIE0)
DI PCINT1 Input CLKI/T0/PCINT0 Input
AIO ADC1/Analog Comparator Negative Input ADC0/Analog Comparator Positive Input
Note:
  1. EXT_CLOCK is 1 when external clock is selected as main clock.