Clock Prescaler Register

Name:: CLKPSR
Offset:: 0x36
Reset:: 0x00000011
Access:: -

Bit7	6	5	4	3	2	1	0
				CLKPS[3:0]
Access				R/W	R/W	R/W	R/W
Reset				0	0	1	1

Bits 3:0 – CLKPS[3:0]: Clock Prescaler Select

Clock Prescaler Select

These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. The division factors are given in the table below.

Table 1. Clock Prescaler Select
CLKPS[3:0]	Clock Division Factor
0000	1
0001	2
0010	4
0011	8 (default)
0100	16
0101	32
0110	64
0111	128
1000	256
1001	Reserved
1010	Reserved
1011	Reserved
1100	Reserved
1101	Reserved
1110	Reserved
1111	Reserved

To avoid unintentional changes of clock frequency, a protected change sequence must be followed to change the CLKPS bits:

Write the signature for change enable of protected I/O register to register CCP
Within four instruction cycles, write the desired value to CLKPS bits

At start-up, CLKPS bits are reset to 0b0011 to select the clock division factor of 8. If the selected clock source has a frequency higher than the maximum allowed the application software must make sure a sufficient division factor is used. To make sure the write procedure is not interrupted, interrupts must be disabled when changing prescaler settings.