AUDIO

The EVK1105 provides two audio solutions, the on-chip ABDAC or an external codec chip that is connected to the UC3 SSC module. While the ABDAC offers audio output only, the codec offers also audio input through a connected microphone. The outputs of both audio solutions can be selected by jumper settings in order to route the signal to the audio jack.

Both audio solutions need an exact clock in order to run at the desired sample rate. Therefore a dedicated crystal is connected to the UC3A device that provides 11.2896 MHz. This clock fits for example fine for a 44.100 kHz sample rate for 16-bit, stereo samples. One sample consists of two channels with 16-bit data each. In order to get a sample rate of 44.100 kHz a clock of 2 x 16 x 44,100 Hz = 1.4112 MHz is needed. The 11.2896 MHz on the EVK1105 is a multiple of this value and is therefore optimal for playing audio at a sample rate of 44.1 kHz.



The TI audio codec is connected to the SSC and TWI module of the UC3A. The management and configuration of the audio codec is done through the TWI interface (I2C address of the codec chip is 0x1A). The SSC is used for the audio input and output. The data transfer follows the I2S specification. More information about the codec is available in the device datasheet from TI (TLV320AIC23B). The audio clock for the codec should be provided from the dedicated on board 11.2896 MHz crystal through the generic clock GCLK[0] (port pin PA07).

Headphones

The headphone output is connected to the jack through a header with jumpers. To route the output of the codec to the headphone jack set the jumpers on J6 in codec position like indicated in the image.



Microphone

A microphone is connected to the codec microphone input line.

Line in/out

The line in/out signals from the codec are available from the header J14. These lines do not have any DC blocking capacitors and should be added if any external low impedance load is connected to these lines.

Pin on header Audio codec pin Name in schematics
1 20 L_LINE_IN
2 19 R_LINE_IN
3 12 L_LINE_OUT
4 13 R_LINE_OUT

ABDAC with external amplifier

The ABDAC output is run through a filter before it is fed into the amplifier. More details about the ABDAC and its usage are available in the document AVR32120: AVR32 ABDAC audio bitstream DAC driver example on the Atmel website. The amplifier has, in contradiction to the codec, a suppression of the DC part in the signal. This makes large capacitors unnecessary in order to drive low impedance loads like headphones and makes therefore this solution ideal for applications that should fit into a small area. More information about the amplifier is available in the datasheet from TI (device TPA6130A2RTJT). The amplifier offers a two wire interface to do configuration and shutdown/power-up. The UC3A is connected to the amplifier through the TWI module and the I2C address of the amplifier is 0b1100000 (0x60).

Headhpone output

To select the amplifier as output for the headphone jack move set the jumpers to the DAC position as indicated in the image.



Channel 0 of the ABDAC is multiplexed with the USART0 lines RTC and CTS with jumpers. The default configuration is set up for the USART and connects the signal lines to the UC3B device. In order to use them as channel 0 with the amplifier set the USART/DAC jumpers.

Hardware configurations

The amplifier offers also an input for an inversed DAC signal. The default hardware setup is configured to use both, the inversed and normal signals. In order to use only one signal line as DAC input for each channel following parts have to be added/removed:

Pinout

Codec

Line in/out

Pin on header Audio codec pin Name in schematics
1 20 L_LINE_IN
2 19 R_LINE_IN
3 12 L_LINE_OUT
4 13 R_LINE_OUT
Audio codec pin UC3A pin name Function
LRCIN PA14 SSC_TX_FRAME_SYNC
BCLK PA15 SSC_TX_CLOCK
DIN PA16 SSC_TX_DATA
LRCOUT PA19 SSC_RX_FRAME_SYNC
DOUT PA17 SSC_RX_DATA
SDIN PA29 TWI_SDA
SCLK PA30 TWI_SCL
XTI/MCLK PA7 GCLK0

Amplifier pinout

Audio amplifier pin UC3A pin name Function
LEFTINM PA3 Left channel (DAC_DATA0)
LEFTINP PA4 Left channel inverted. (DAC_DATA0N
RIGHTINM PA23 Right channel (DAC_DATA1)
RIGHTINP PA24 Right channel inverted. (DAC_DATA1N)
SDA PA29 TWI SDA
SCL PA30 TWI SCL
Figure 1. Schematics