The Direct Memory Access Controller (DMAC) can transfer data between memories and peripherals, and thus off-load these tasks from the CPU. It enables high data transfer rates (using AHB clock) with minimum CPU intervention and frees up CPU time. This will allow the CPU to sleep for a longer time and thus reduce the power consumption.

A complete DMA read and write operation between memories and/or peripherals is called a DMA transaction. DMA reads data from the source address before writing to the destination address. A new data is read when the previous write operation is completed.

The transaction is initiated by a trigger and uses a DMA channel. The DMA trigger source can be application software, peripheral, or events from Event System (EVSYS).

Each read and write operation are done in blocks. The size of transfer is controlled by the block transfer size and is configured in the software. The size of the block can be from 1 to 64K beats. The beat can be byte, half-word, or word