In Master mode, the Slave Select Disable bit in Control Register B (SSD bit in SPIn.CTRLB) controls how the SPI uses the SS pin.
If SSD in SPIn.CTRLB is ‘0
’, the SPI can use the
SS pin to transition from Master to Slave mode. This
allows multiple SPI masters on the same SPI bus.
If SSD in SPIn.CTRLB is ‘0
’, and the
SS pin is configured as an output pin, it can be used as
a regular I/O pin or by other peripheral modules, and will not affect the SPI
system.
If SSD in SPIn.CTRLB is ‘1
’, the SPI does not use the
SS pin, and it can be used as a regular I/O pin, or by
other peripheral modules.
0
’, and the
SS is configured as an input pin, the
SS pin must be held high to ensure master SPI operation. A low
level will be interpreted as another master is trying to take control of the bus. This will
switch the SPI into Slave mode, and the hardware of the SPI will perform the following
actions: SS Configuration | SS Pin-Level | Description |
---|---|---|
Input | High | Master activated (selected) |
Low | Master deactivated, switched to Slave mode | |
Output | High | Master activated (selected) |
Low |