The Buffer Mode is enabled by setting the BUFEN bit in SPI.CTRLB. The BUFWR
bit in SPI.CTRLB has no effect in Master mode. In Buffer Mode the system is double buffered
in the transmit direction and triple buffered in the receive direction. This influences the
data handling the following ways:
- 1.New bytes to be sent can be written
to the data register (DATA) as long as the Data Register Empty Interrupt Flag (DREIF)
in the Interrupt Flag Register (INTFLAGS) is set. The first write will be transmitted
right away and a following write will go to the transmit buffer register.
- 2.A received byte is placed in a
two-entry RX FIFO comprised of the First and Second Receive Buffer Registers
immediately after the transmission is completed.
- 3.The Data Register is used to read
from the RX FIFO. The RX FIFO must be read at least every second transfer to avoid
any loss of data.
If both the Shift Register and the Transmit Buffer Register becomes empty, the
Transfer Complete Interrupt Flag (TXCIF) in the Interrupt Flags Register (INTFLAGS) will be
set. This will cause the corresponding interrupt to be executed if this interrupt and the
global interrupts are enabled. Setting the Transfer Complete Interrupt Enable (TXCIE) in
the Interrupt Control Register (INTCTRL) enables the Transfer Complete Interrupt.