Register Synchronization Categories

Most of the IO registers need to be synchronized to the asynchronous TCD core clock domain. This is done in different ways for different register categories:

See Table 1 for categorized registers.

Command and Enable Registers

Because of synchronization between the clock domains it is only possible to change the Enable bits while the Enable Ready bit (ENRDY) in the Status register (TCD.STATUS) is '1'.

The Control E register commands (TCD.CTRLE) are automatically synchronized to the TCD core domain when the TCD is enabled and as long as there not a synchronization ongoing already. Check in the Status register if the Command Ready bit (CCMDRDY) is '1' (TCD.STATUS) to ensure that it is possible to write a new command. TCD.CTRLE is a strobe register that will clear itself when the command is done.

The Control E register commands are:
  • Synchronize at end of TCD cycle: synchronizes all doubled buffered registers to TCD clock domain at the end of the TCD cycle
  • Synchronize: synchronized all doubled buffered registers to TCD clock domain when the command is synchronized to TCD clock domain
  • Restart: Restarts the TCD counter
  • Software Capture A: Capture TCD counter value to TCD.CAPTUREA
  • Software Capture B: Capture TCD counter value to TCD.CAPTUREB

Double-Buffered Registers

The doubled-buffered registers can be updated in normal IO writes while the TCD is enabled and no synchronization between the two clock domains is ongoing. Check that the CMDRDY bit in TCD.STATUS is '1' to ensure that it is possible to update the doubled buffered IO registers. The values will be synchronized to the TCD core domain when a synchronization command is sent or when the TCD is enabled.

Static Registers

The static registers are kept static whenever the TCD is enabled. That means that these registers must be configured before enabling the TCD. It is not possible to write to these registers as long as the TCD is enabled. To see if the TCD is enabled, check if ENABLE in TCD.CTRLA is reading '1'.

Normal IO and Status Registers

The read-only registers inform about synchronization status and values synchronized from the core domain. The reset of these registers and normal IO registers are not constrained by any synchronization between the domains.

Table 1. Categorization of Registers
Enable and Command registers Doubled-buffered registers Static registers Read-only registers Normal IO registers
TCD.CTRLA (ENABLE bit) TCD.DLYCTRL TCD.CTRLA (All bits Except ENABLE bit) TCD.STATUS TCD.INTCTRL
TCD.CTRLE TCD.DLYVAL TCD.CTRLB TCD.CAPTUREA TCD.INTFLAGS
  TCD.DITCTRL TCD.CTRLC TCD.CAPTUREB  
  TCD.DITVAL TCD.CTRLD    
  TCD.DBGCTRL TCD.EVCTRLA    
  TCD.CMPASET TCD.EVCTRLB    
  TCD.CMPACLR TCD.INPUTCTRLA    
  TCD.CMPBSET TCD.INPUTCTRLB    
  TCD.CMPBCLR TCD.FAULTCTRL