I/O Multiplexing

Each pin is by default controlled by the PORT as a general purpose I/O and alternatively it can be assigned to one of the peripheral functions. The following table describes the peripheral signals multiplexed to the PORT I/O pins.

Table 1. PORT Function Multiplexing
14-pin 8-pin Pin name Special INT(3) ADC(3) AC USART Timer Programming(8)
1 1(1) VCC              
3 3 PA[1](5)   PCINT1 ADC1 AIN1   OC0B TPIDATA
4 4 PA[2] RESET PCINT2         RESET
5 - PA[3](9)   PCINT3       OC0A  
6 - PA[4](9)   PCINT4       ICP0  
7 - PA[5](5)(9)   PCINT5 ADC2     OC0B  
8 - PA[6]   PCINT6 ADC3        
9 - PA[7]   PCINT7          
10 - PB[0]   PCINT8 ADC4        
11 5 PB[1](6) CLKO PCINT9/INT0 ADC5   XCK0 OC0A  
12 6 PB[2](7)   PCINT10 ADC6   TxD0 ICP0  
13 7 PB[3](4)(9)   PCINT11 ADC7 ACO RxD0 T0  
14 8 GND              
  1. 1.On the 8-pin UDFN package, the thermal pad should not be connected as well.
  2. 2.Priority of CLKI is higher than ADC0. When EXT_CLK is enabled, ADC channel will not work and DIDR0 will not disable the digital input buffer.
  3. 3.When both PCINT and the corresponding ADC channel are enabled, the digital input buffer will not be disabled.
  4. 4.When ACO is enabled, ADC, TC and USART RX inputs are not disabled.
  5. 5.When OC0B is enabled, ADC and AC will continue to receive inputs on that channel if enabled.
  6. 6.When CLKO is enable in PB[1], OCA will get lower priority.
  7. 7.When USART is enabled, the users must ensure that ADC channel corresponding to the TxD0 pin is not used. Because DIDR0 register will only control the input buffer, not the output part.
  8. 8.During reset/external programming, all pins are treated as inputs and outputs are disabled.
  9. 9.Alternative location when enabling T/C Remap