Timer2 Module

The Timer2 module is a 8-bit timer that incorporates the following features:

See Figure 1 for a block diagram of Timer2. See table below for the clock source selections.

Important: References to module Timer2 apply to all the even numbered timers on this device. (Timer2, Timer4, etc.)
Figure 1. Timer2 with Hardware Limit Timer (HLT) Block Diagram
Note:
  1. 1.Signal to the CCP to trigger the PWM pulse.
  2. 2.See TxRST for external Reset sources.
Table 1. Clock Source Selection
CS<4:0> Clock Source
Timer2 Timer4 Timer6
11111-11000 Reserved Reserved Reserved
10111 CLC8_out CLC8_out CLC8_out
10110 CLC7_out CLC7_out CLC7_out
10101 CLC6_out CLC6_out CLC6_out
10100 CLC5_out CLC5_out CLC5_out
10011 CLC4_out CLC4_out CLC4_out
10010 CLC3_out CLC3_out CLC3_out
10001 CLC2_out CLC2_out CLC2_out
10000 CLC1_out CLC1_out CLC1_out
01111-01001 Reserved Reserved Reserved
01000 ZCD_OUT ZCD_OUT ZCD_OUT
00111 CLKREF_OUT CLKREF_OUT CLKREF_OUT
00110 SOSC SOSC SOSC
00101 MFINTOSC (31 kHz) MFINTOSC (31 kHz) MFINTOSC (31 kHz)
00100 LFINTOSC LFINTOSC LFINTOSC
00011 HFINTOSC HFINTOSC HFINTOSC
00010 FOSC FOSC FOSC
00001 FOSC/4 FOSC/4 FOSC/4
00000 Pin selected by T2INPPS Pin selected by T4INPPS Pin selected by T6INPPS