CLCxGLS2

CLCx Gate3 Logic Select Register
Name:
CLCxGLS2
Address:
0xE2F,0xE39,0xE43,0xE4D,0xE57,0xE61,0xE6B,0xE75
Reset:
Access:
Bit76543210
G3D4TG3D4NG3D3TG3D3NG3D2TG3D2NG3D1TG3D1N
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Resetxxxxxxxx

Bits 0, 2, 4, 6 – G3DyN

dyN: Gate3 Data 'y' Negated (inverted) bit
ValueDescription
1 dyN is gated into g3
0 dyN is not gated into g3

Bits 1, 3, 5, 7 – G3DyT

dyT: Gate3 Data 'y' True (non-inverted) bit
ValueDescription
1 dyT is gated into g3
0 dyT is not gated into g3