TXxSTA

Transmit Status and Control Register

Note:
  1. 1.SREN and CREN bits override TXEN in Sync mode.
Name:
TXxSTA
Address:
0xF9D,0xE99
Reset:
Access:
Bit76543210
CSRCTX9TXENSYNCSENDBBRGHTRMTTX9D
AccessR/WR/WR/WR/WR/WR/WROR/W
Reset00000010

Bit 7 – CSRC: Clock Source Select bit

Clock Source Select bit

ValueNameDescription
1 SYNC= 1

Master mode (clock generated internally from BRG)

0 SYNC= 1

Slave mode (clock from external source)

X SYNC= 0

Don't care

Bit 6 – TX9: 9-bit Transmit Enable bit

9-bit Transmit Enable bit

ValueDescription
1

Selects 9-bit transmission

0

Selects 8-bit transmission

Bit 5 – TXEN: Transmit Enable bit

Transmit Enable bit

Enables transmitter(1)

ValueDescription
1

Transmit enabled

0

Transmit disabled

Bit 4 – SYNC: EUSART Mode Select bit

EUSART Mode Select bit

ValueDescription
1

Synchronous mode

0

Asynchronous mode

Bit 3 – SENDB: Send Break Character bit

Send Break Character bit

ValueNameDescription
1 SYNC= 0

Send Sync Break on next transmission (cleared by hardware upon completion)

0 SYNC= 0

Sync Break transmission disabled or completed

X SYNC= 1

Don't care

Bit 2 – BRGH: High Baud Rate Select bit

High Baud Rate Select bit

ValueNameDescription
1 SYNC= 0

High speed, if BRG16 = 1, baud rate is baudclk/4; else baudclk/16

0 SYNC= 0

Low speed

X SYNC= 1

Don't care

Bit 1 – TRMT: Transmit Shift Register (TSR) Status bit

Transmit Shift Register (TSR) Status bit

ValueDescription
1

TSR is empty

0

TSR is not empty

Bit 0 – TX9D: Ninth bit of Transmit Data

Ninth bit of Transmit Data

Can be address/data bit or a parity bit.