Logic cell output data, after LCPOL. Sampled from
CLCxOUT
Configurable Logic Cell Positive Edge Going Interrupt Enable
bit
Value | Description |
---|
1 |
CLCxIF will be set when a rising edge occurs on
CLCxOUT |
0 |
Rising edges on CLCxOUT have no effect on
CLCxIF |
Configurable Logic Cell Negative Edge Going Interrupt Enable
bit
Value | Description |
---|
1 |
CLCxIF will be set when a falling edge occurs on
CLCxOUT |
0 |
Falling edges on CLCxOUT have no effect on
CLCxIF |
Configurable Logic Cell Functional Mode Selection
bits
Value | Description |
---|
111 |
Cell is 1-input transparent latch with Set and
Reset |
110 |
Cell is J-K flip-flop with
Reset |
101 |
Cell is 2-input D flip-flop with
Reset |
100 |
Cell is 1-input D flip-flop with Set and
Reset |
011 |
Cell is S-R latch |
010 |
Cell is 4-input AND |
001 |
Cell is OR-XOR |
000 |
Cell is AND-OR |