SPI Mode Requirements

Table 1.
Standard Operating Conditions (unless otherwise stated)
Param No. Sym. Characteristic Min. Typ. † Max. Units Conditions
SP70*

TSSL2SCH,

TSSL2SCL

SS↓ to SCK↓ or SCK↑ input 2.25*TCY ns  
SP71* TSCH SCK input high time (Slave mode) TCY + 20 ns  
SP72* TSCL SCK input low time (Slave mode) TCY + 20 ns  
SP73*

TDIV2SCH,

TDIV2SCL

Setup time of SDI data input to SCK edge 100 ns  
SP74*

TSCH2DIL,

TSCL2DIL

Hold time of SDI data input to SCK edge 100 ns  
SP75* TDOR SDO data output rise time 10 25 ns 3.0V≤VDD≤5.5V
25 50 ns 1.8V≤VDD≤5.5V
SP76* TDOF SDO data output fall time 10 25 ns  
SP77* TSSH2DOZ SS↑ to SDO output high-impedance 10 50 ns  
SP78* TSCR SCK output rise time (Master mode) 10 25 ns 3.0V≤VDD≤5.5V
25 50 ns 1.8V≤VDD≤5.5V
SP79* TSCF SCK output fall time (Master mode) 10 25 ns  
SP80*

TSCH2DOV,

TSCL2DOV

SDO data output valid after SCK edge 50 ns 3.0V≤VDD≤5.5V
145 ns 1.8V≤VDD≤5.5V
SP81*

TDOV2SCH,

TDOV2SCL

SDO data output setup to SCK edge 1 TCY ns  
SP82* TSSL2DOV SDO data output valid after SS↓ edge 50 ns  
SP83*

TSCH2SSH,

TSCL2SSH

SS ↑after SCK edge 1.5 TCY + 40 ns  

* - These parameters are characterized but not tested.

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

Figure 1. SPI Master Mode Timing (CKE = 0, SMP = 0)
Note: Refer to Figure 1 for load conditions.
Figure 2. SPI Master Mode Timing (CKE = 1, SMP = 1)
Note: Refer to Figure 1 for load conditions.
Figure 3. SPI Slave Mode Timing (CKE = 0)
Note: Refer to Figure 1 for load conditions.
Figure 4. SPI Slave Mode Timing (CKE = 1)
Note: Refer to Figure 1 for load conditions.