The Serial Peripheral Interface (SPI) is connected through four digital signals; MOSI, MISO, SCK, and CS. The SPI is set to operate in slave mode, meaning that the target device must be set to master mode. The active low CS (Chip Select) line indicates to the SPI that it should expect data to be received and/or sent. If the master expects to receive data from the slave, it must poll for them by initiating a transfer. All pins are tri-stated until the interface is activated from the PC and the CS line is driven low.
It is possible to configure the mode (clock phase and data setup) of the SPI module. Valid settings are 0-3. The bit count for each transfer can also be set between 5 and 8 bits per transfer.
In normal operation, DMA will automatically buffer incoming data transfers. It is also possible to enable timestamping to get a more accurate timing of incoming data. Note that the timestamping will add an overhead to each data transfer, and a lower maximal throughput and a longer required inter-byte delay is expected. For sending data to the target device DMA is always used.