Receive Complete Interrupt Enable
The bit enables the
Receive Complete Interrupt (interrupt vector RXC). The enabled interrupt will be
triggered when RXCIF in the USARTn.STATUS register is set.
Transmit Complete Interrupt Enable
This bit enables the
Transmit Complete Interrupt (interrupt vector TXC). The enabled interrupt will be
triggered when the TXCIF in the USARTn.STATUS register is set.
Data Register Empty Interrupt Enable
This bit enables the
Data Register Empty Interrupt (interrupt vector DRE). The enabled interrupt will be
triggered when the DREIF in the USART.STATUS register is set.
Receiver Start Frame Interrupt Enable
Writing a '1' to
this bit enables the Start Frame Detector to generate an interrupt on interrupt
vector RXC when a start-of-frame condition is detected.
Loop-back Mode Enable
Writing this bit to
'1' enables an internal connection between the TxD and RxD
pin.
Auto-baud Error Interrupt Enable
Writing this bit to
'1' enables the auto-baud error interrupt on interrupt vector RXC. The enabled
interrupt will trigger for conditions where the ISFIF flag is
set.
RS-485
Mode
These bits enable
the RS-485 and select the operation mode.
Value | Name | Description |
---|
0x0 |
OFF |
Disabled. |
0x1 |
EXT |
Enables
RS-485 mode with control of an external line driver through a dedicated
Transmit Enable (TE) pin. |
0x2 |
INT |
Enables
RS-485 mode with control of the internal USART
transmitter. |
0x3 |
- |
Reserved. |