This mode can be used to generate a pulse with a duration that is defined by the Compare register (TCBn.CCMP), every time a rising or falling edge is observed on a connected event channel.
When the counter is stopped, the output pin is driven to low. If an event is detected on the connected event channel, the timer will reset and start counting from zero to TOP while driving its output high. The RUN bit in the STATUS register can be read to see if the counter is counting or not. When the counter register reaches the CCMP register value, the counter will stop and the output pin will go low for at least one prescaler cycle. If a new event arrives during this time, that event will be ignored. The following figure shows an example waveform. There is a two clock cycle delay from when the event is received until the output is set high. If the ASYNC bit in TCBn.CTRLB is written to '1', an asynchronous edge detector is used for input events to give immediate action. When the EDGE bit of the TCBn.EVCTRL register is written to '1', any edge can trigger the start of the counter. If the EDGE bit is '0', only positive edges will trigger the start.
The counter will start as soon as the module is enabled, even without triggering event. This is prevented by writing TOP to the counter register.
Similar behavior is seen if the EDGE bit in the TCBn.EVCTRL register is '1' while the module is enabled. Writing TOP to the Counter register prevents this as well.
It is not recommended to change configuration while the module is enabled.
If the ASYNC bit in TCBn.CTRLB is '0', the event pulse needs to be longer than one system clock cycle in order to ensure edge detection.