Frequency Considerations

In theory, digital CMOS logic consumes power only when the logical signals or the clock signals are toggling, hence keeping the clock frequencies as low as possible is critical for reducing the power consumption. However, lowering the system frequency will give a penalty when it comes to responsiveness. In some cases, where the amount of time spent in Active mode is small, it may be better to run at a high frequency as it will enable for the device to be put back to sleep faster.

For some of the peripherals on devices from the SAM D and SAM L series the generic clock can be prescaled after reaching the peripheral. This feature enables for more clock flexibility but it also requires more power. When the frequency is prescaled in the clock generator instead of in the peripheral, the generic clock propagated to the peripheral is of a lower frequency. A lower frequency means less toggling between the clock generator and the peripheral, which will lower the power consumption.