Sleep Modes

In many applications, the processor does not run continuously and peripherals may be idle much of the time. For instance the application might be waiting for some external trigger before it starts using the processor and peripherals. By taking advantage of the various sleep modes available for devices from the SAM D and SAM L series, one can reduce the power consumption significantly by enabling the device to sleep while waiting.

Devices in the SAM D series has two sleep modes, IDLE and STANDBY, where the Idle mode is divided into three levels; IDLE0, IDLE1, and IDLE2. In the Idle sleep mode the CPU clock is stopped and dependent on the Idle level, additional synchronous clocks are stopped. In STANDBY all clocks are stopped, except for those who are configured to run in standby. For further information about the sleep modes for devices in the SAM D series, refer to their datasheets.

Devices in the SAM L series have four sleep modes; IDLE, STANDBY, BACKUP, and OFF. In IDLE only the CPU clock is stopped. In STANDBY the CPU clock as well as the main clock (MCLK) is stopped, and both regulators and SRAM are in low power mode. The peripheral clocks (GCLK) are only run if requested by the peripheral. In BACKUP all clocks are stopped and SRAM will not be able to retain any data. In OFF the entire device is powered off, and it can only be woken up by an external or power on reset. For further information about the sleep modes in for devices in the SAM L series, refer to their datasheets.

Sleep is entered by issuing the Wait For Interrupt (WFI) instruction. Before entering sleep, the sleep mode must be chosen. For devices in the SAM D series the sleep mode is configured by writing the Sleep Deep bit in the ARM® Cortex® System Control register (SCR.SLEEPDEEP). If SCR.SLEEPDEEP is configured to Idle sleep mode, the Idle Mode Configuration bit group in the Sleep Mode register (SLEEP.IDLE) must also be configured.

For devices in the SAM L series the sleep mode is configured by writing the Sleep Mode bit group in the Sleep Configuration register (SLEEPCFG.SLEEPMODE).

If an application is fully interrupt driven, the device can return to sleep even faster if the Sleep On Exit bit in the ARM Cortex System Control register (SCR.SLEEPONEXIT) is set.

For this and some of the following subsections a temperature monitoring application will be used as an example in order to make it easier to understand some of the ultra low power techniques presented in this application note.

Consider a simple application where the temperature in a room is monitored using a temperature sensor with the analog-to-digital converter (ADC). In order to reduce the power consumption the CPU would be put to sleep and wake up periodically on interrupts from a real time counter (RTC). The measured sensor data is checked against a predefined threshold to decide on further action. If the data does not exceed the threshold, the CPU will be put back to sleep waiting for the next RTC interrupt.