ADC Acquisition Requirements

For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in ADC Acquisition Requirements. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), refer to ADC Acquisition Requirements. The maximum recommended impedance for analog sources is 10 kΩ. As the source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an ADC acquisition must be completed before the conversion can be started. To calculate the minimum acquisition time, Acquisition Time Example may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the ADC). The 1/2 LSb error is the maximum error allowed for the ADC to meet its specified resolution.

Acquisition Time Example

Note:
  1. 1.The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
  2. 2.The charge holding capacitor (CHOLD) is not discharged after each conversion.
  3. 3.The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin leakage specification.
Figure 1. Analog Input Model
Figure 2. ADC Transfer Function
Parent topic: (ADC2) Analog-to-Digital Converter with Computation Module