In this mode, either the duty cycle or period (depending on polarity) of the input signal can be acquired relative to the SMT clock. The CPW register is updated on a falling edge of the signal, and the CPR register is updated on a rising edge of the signal, along with the SMTxTMR resetting to 0x000001. In addition, the SMTxGO bit is reset on a rising edge when the SMT is in single acquisition mode. See figures below.
Figure 1. Period and Duty-Cycle, Repeat Acquisition Mode Timing Diagram
Figure 2. Period and Duty-Cycle, Single Acquisition Mode Timing Diagram
