SMTxTMR
SMT Timer Register
Bit23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
TMRU[7:0] | |||||||
AccessR/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
Reset0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TMRH[7:0] | |||||||
AccessR/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
Reset0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TMRL[7:0] | |||||||
AccessR/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
Reset0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Upper byte of the SMT timer register
High byte of the SMT timer register
Lower byte of the SMT timer register