Each peripheral has an xxxPPS register with which the input pin to the peripheral is selected. Not all ports are available for input as shown in the following table.
Multiple peripherals can operate from the same source simultaneously. Port reads always return the pin level regardless of peripheral PPS selection. If a pin also has analog functions associated, the ANSEL bit for that pin must be cleared to enable the digital input buffer.
| Peripheral | PPS Input Register | Default Pin Selection at POR | Register Reset Value at POR | PORT From Which Input Is Available | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| Interrupt 0 | INT0PPS | RB0 | 0x08 | A | B | — | — | — | — | — | — |
| Interrupt 1 | INT1PPS | RB1 | 0x09 | — | B | C | — | — | — | — | — |
| Interrupt 2 | INT2PPS | RB2 | 0x0A | — | B | — | D | — | — | — | — |
| Interrupt 3 | INT3PPS | RB3 | 0x0B | — | B | — | — | E | — | — | — |
| Timer0 Clock | T0CKIPPS | RA4 | 0x04 | A | B | — | — | — | — | — | — |
| Timer1 Clock | T1CKIPPS | RC0 | 0x10 | — | — | C | D | — | — | — | — |
| Timer1 Gate | T1GPPS | RB5 | 0x0D | — | B | C | — | — | — | — | — |
| Timer3 Clock | T3CKIPPS | RB5 | 0x0D | — | B | C | — | — | — | — | — |
| Timer3 Gate | T3GPPS | RA5 | 0x05 | A | — | C | — | — | — | — | — |
| Timer5 Clock | T5CKIPPS | RD1 | 0x19 | — | — | — | D | E | — | — | — |
| Timer5 Gate | T5GPPS | RG4 | 0x34 | — | — | — | — | E | — | G | — |
| Timer7 Clock | T7CKIPPS | RG4 | 0x34 | — | — | — | — | E | — | G | — |
| Timer7 Gate | T7GPPS | RD1 | 0x19 | — | — | — | D | E | — | — | — |
| Timer2 Clock | T2INPPS | RA1 | 0x01 | A | — | C | — | — | — | — | — |
| Timer4 Clock | T4INPPS | RE4 | 0x24 | — | B | — | — | E | — | — | — |
| Timer6 Clock | T6INPPS | RC1 | 0x11 | — | B | C | — | — | — | — | — |
| Timer8 Clock | T8INPPS | RA0 | 0x00 | A | — | — | — | E | — | — | — |
| ADC Conversion Trigger | ADACTPPS | RH1 | 0x39 | — | — | C | — | — | — | — | H |
| CCP1 | CCP1PPS | RE5 | 0x25 | — | — | C | — | E | — | — | — |
| CCP2 | CCP2PPS | RE4 | 0x24 | — | — | C | — | E | — | — | — |
| CCP3 | CCP3PPS | RE6 | 0x26 | — | — | C | — | E | — | — | — |
| CCP4 | CCP4PPS | RG3 | 0x33 | — | — | — | — | E | — | G | — |
| CCP5 | CCP5PPS | RG4 | 0x34 | — | — | — | — | E | — | G | — |
| SMT1 Window | SMT1WINPPS | RE6 | 0x26 | — | — | C | — | E | — | — | — |
| SMT1 Signal | SMT1SIGPPS | RE7 | 0x27 | — | — | C | — | E | — | — | — |
| SMT2 Window | SMT2WINPPS | RE6 | 0x26 | — | — | C | — | E | — | — | — |
| SMT2 Signal | SMT2SIGPPS | RE7 | 0x27 | — | — | C | — | E | — | — | — |
| CWG | CWG1PPS | RC2 | 0x12 | A | — | C | — | — | — | — | — |
| DSM Carrier Low | MDCARLPPS | RD3 | 0x1B | — | — | — | D | — | — | — | H |
| DSM Carrier High | MDCARHPPS | RD4 | 0x1C | — | — | — | D | — | — | — | H |
| DSM Source | MDSRCPPS | RD5 | 0x1D | — | — | — | D | — | — | — | H |
| MSSP1 Clock | SSP1CLKPPS | RC3 | 0x13 | — | B | C | — | — | — | — | — |
| MSSP1 Data | SSP1DATPPS | RC4 | 0x14 | — | B | C | — | — | — | — | — |
| MSSP1 Slave Select | SSP1SSPPS | RF7 | 0x2F | — | B | — | — | — | — | F | — |
| MSSP2 Clock | SSP2CLKPPS | RD6 | 0x1E | — | B | — | D | — | — | — | — |
| MSSP2 Data | SSP2DATPPS | RD5 | 0x1D | — | B | — | D | — | — | — | — |
| MSSP2 Slave Select | SSP2SSPPS | RD7 | 0x1F | — | B | — | D | — | — | — | — |
| EUSART1 Receive | RX1PPS | RC7 | 0x17 | — | — | C | D | — | — | — | — |
| EUSART1 Clock | CK1PPS | RC6 | 0x16 | — | — | C | D | — | — | — | — |
| EUSART2 Receive | RX2PPS | RG2 | 0x32 | — | — | — | D | — | — | G | — |
| EUSART2 Clock | CK2PPS | RG1 | 0x31 | — | — | — | D | — | — | G | — |
| EUSART3 Receive | RX3PPS | RE1 | 0x21 | — | B | — | — | E | — | — | — |
| EUSART3 Clock | CK3PPS | RE0 | 0x20 | — | B | — | — | E | — | — | — |
| EUSART4 Receive | RX4PPS | RC1 | 0x11 | — | B | — | C | — | — | — | — |
| EUSART4 Clock | CK4PPS | RC0 | 0x10 | — | B | — | C | — | — | — | — |
| EUSART5 Receive | RX5PPS | RE3 | 0x23 | — | — | — | — | E | — | G | — |
| EUSART5 Clock | CK5PPS | RE2 | 0x22 | — | — | — | — | E | — | G | — |