PIR4
Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RC5IF | TX5IF | RC4IF | TX4IF | RC3IF | TX3IF | ||
Access | R | R | R | R | R | R | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 |
EUSART5 Receive Interrupt Flag bit
Value | Description |
---|---|
1 | The EUSART5 receive buffer, RC5REG, is full (cleared by reading RC5REG) |
0 | The EUSART5 receive buffer is empty |
EUSART5 Transmit Interrupt Flag bit
Value | Description |
---|---|
1 | The EUSART5 transmit buffer, TX5REG, is empty (cleared by writing TX5REG) |
0 | The EUSART5 transmit buffer is full |
EUSART4 Receive Interrupt Flag bit
Value | Description |
---|---|
1 | The EUSART4 receive buffer, RC4REG, is full (cleared by reading RC4REG) |
0 | The EUSART4 receive buffer is empty |
EUSART4 Transmit Interrupt Flag bit
Value | Description |
---|---|
1 | The EUSART4 transmit buffer, TX4REG, is empty (cleared by writing TX4REG) |
0 | The EUSART4 transmit buffer is full |
EUSART3 Receive Interrupt Flag bit
Value | Description |
---|---|
1 | The EUSART3 receive buffer, RC3REG, is full (cleared by reading RC3REG) |
0 | The EUSART3 receive buffer is empty |
EUSART3 Transmit Interrupt Flag bit
Value | Description |
---|---|
1 | The EUSART3 transmit buffer, TX3REG, is empty (cleared by writing TX3REG) |
0 | The EUSART3 transmit buffer is full |