Large areas of data memory require an efficient addressing scheme to make rapid access to any address possible. Ideally, this means that an entire address does not need to be provided for each read or write operation. For PIC18 devices, this is accomplished with a RAM banking scheme. This divides the memory space into 16 contiguous banks of 256 bytes. Depending on the instruction, each location can be addressed directly by its full 12-bit address, or an 8-bit low-order address and a 4-bit Bank Pointer.
Most instructions in the PIC18 instruction set make use of the Bank
Pointer, known as the Bank Select Register (BSR).
This SFR holds the four Most Significant bits of a location’s address; the instruction
itself includes the eight Least Significant bits. Only the four lower bits of the BSR are
implemented (BSR<3:0>). The upper four bits are unused; they will always read ‘0’ and
cannot be written to. The BSR can be loaded directly by using the MOVLB
instruction.
The value of the BSR indicates the bank in data memory; the eight bits in the instruction show the location in the bank and can be thought of as an offset from the bank’s lower boundary. The relationship between the BSR’s value and the bank division in data memory is shown in the figure below.
Since up to 16 registers may share the same low-order address, the user must always be careful to ensure that the proper bank is selected before performing a data read or write. For example, writing what should be program data to an 8-bit address of F9h while the BSR is 0Fh will end up resetting the Program Counter.
While any bank can be selected, only those banks that are actually implemented can be read or written to. Writes to unimplemented banks are ignored, while reads from unimplemented banks will return ‘0’s. Even so, the STATUS register will still be affected as if the operation was successful. The data memory maps in the following figure indicate which banks are implemented.
In the core PIC18 instruction set, only the MOVFF
instruction fully specifies the 12-bit address of the source and target registers. This
instruction ignores the BSR completely when it executes. All other instructions include
only the low-order address as an operand and must use either the BSR or the Access Bank to
locate their target registers.
