PPS Outputs

Each I/O pin has an RxyPPS register with which the pin output source is selected. With few exceptions, the port TRIS control associated with that pin retains control over the pin output driver. Peripherals that control the pin output driver as part of the peripheral operation will override the TRIS control as needed. These peripherals include:

Although every pin has its own RxyPPS peripheral selection register, the selections are identical for every pin as shown in the following table.

Important: The notation “Rxy” is a place holder for the pin identifier. The 'x' holds the place of the PORT letter and the 'y' holds the place of the bit number. For example, Rxy = RA0 for the RA0PPS register.
Table 1. Peripheral PPS Output Selection Codes
RxyPPS Pin Rxy Output Source PORT To Which Output Can Be Directed
0x21 ADGRDB C H
0x20 ADGRDA C H
0x1F DSM1 C H
0x1E CLKR C H
0x1D TMR0 B C
0x1C MSSP2 (SDO/SDA) B D
0x1B MSSP2 (SCK/SCL) B D
0x1A MSSP1 (SDO/SDA) B C
0x19 MSSP1 (SCK/SCL) B C
0x18 CMP3 F G
0x17 CMP2 F G
0x16 CMP1 F G
0x15 EUSART5 (DT) E G
0x14 EUSART5 (TX/CK) E G
0X13 EUSART4 (DT) B C
0x12 EUSART4 (TX/CK) B C
0x11 EUSART3 (DT) B E
0x10 EUSART3 (TX/CK) B E
0x0F EUSART2 (DT) D G
0x0E EUSART2 (TX/CK) D G
0x0D EUSART1 (DT) C D
0x0C EUSART1(TX/CK) C D
0x0B PWM7 C E
0x0A PWM6 C E
0x09 CCP5 E G
0x08 CCP4 E G
0x07 CCP3 C E
0x06 CCP2 C E
0x05 CCP1 C E
0x04 CWG1D E G
0x03 CWG1C C E
0x02 CWG1B E G
0x01 CWG1A C E
0x00 LATxy A B C D E F G H