PCON0
Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STKOVF | STKUNF | WDTWV | RWDT | RMCLR | RI | POR | BOR |
AccessR/W/HS | R/W/HS | R/W/HC | R/W/HC | R/W/HC | R/W/HC | R/W/HC | R/W/HC |
Reset0 | 0 | 1 | 1 | 1 | 1 | 0 | q |
Stack Overflow Flag bit
Value | Description |
---|---|
1 |
A Stack
Overflow occurred (more CALL s than fit on the
stack) |
0 |
A Stack
Overflow has not occurred or set to ‘0 ’ by
firmware |
Stack Underflow Flag bit
Value | Description |
---|---|
1 |
A Stack
Underflow occurred (more RETURN s than
CALL s) |
0 |
A Stack
Underflow has not occurred or set to ‘0 ’ by
firmware |
Watchdog Window Violation Flag bit
Value | Description |
---|---|
1 |
A WDT window
violation has not occurred or set to ‘1 ’ by
firmware |
0 |
A |
WDT Reset Flag bit
Value | Description |
---|---|
1 |
A WDT
overflow/time-out Reset has not occurred or set to ‘1 ’ by
firmware |
0 |
A WDT
overflow/time-out Reset has occurred (set to ‘0 ’ in hardware when
a WDT Reset occurs) |
MCLR Reset Flag bit
Value | Description |
---|---|
1 |
A
MCLR Reset has not occurred or set to
‘1 ’ by firmware |
0 |
A
MCLR Reset has occurred (set to ‘0 ’
in hardware when a MCLR Reset
occurs) |
RESET
Instruction Flag bit
Value | Description |
---|---|
1 |
A
RESET instruction has not been executed or set to
‘1 ’ by firmware |
0 |
A
RESET instruction has been executed (set to
‘0 ’ in hardware upon executing a RESET
instruction) |
Power-on Reset Status bit
Value | Description |
---|---|
1 |
No Power-on
Reset occurred or set to ‘1 ’ by
firmware |
0 |
A Power-on
Reset occurred (set to ‘0 ’ in hardware when a Power-on Reset
occurs) |
Brown-out Reset Status bit
Value | Description |
---|---|
1 |
No Brown-out
Reset occurred or set to ‘1 ’ by
firmware |
0 |
A Brown-out
Reset occurred (set to ‘0 ’ in hardware when a Brown-out Reset
occurs) |