Conversion Clock

The conversion clock source is software selected with the ADCS bit. When ADCS = 1 the ADC clock source is an internal fixed-frequency clock referred to as FRC. When ADCS = 0 the ADC clock frequencies are derived from F_OSC. The ADCLK register selects one of 64 possible clock options from F_OSC/2 to F_OSC/128:

F_OSC/2
F_OSC/4
F_OSC/6
F_OSC/8
F_OSC/10
...
F_OSC/128

The time to complete one bit conversion is defined as the T_AD. One full 10-bit conversion requires 11.5 T_AD periods as shown in Figure 1.

For correct conversion, the appropriate T_AD specification must be met. Refer to the "ADC Timing Specifications" for more information. The "ADC Clock Period" table below gives examples of appropriate ADC clock selections.

Important:

1.Except for the FRC clock source, any changes in the system clock frequency will change the ADC clock frequency, which may adversely affect the ADC result.
2.The internal control logic of the ADC runs off of the clock selected by ADCS. When the ADCS is set to ‘1’ (ADC runs on FRC), there may be unexpected delays in operation when setting ADC control bits.

Table 1. ADC Clock Period (T_AD) Vs. Device Operating Frequencies^(1,4)
ADC Clock Period (T_AD)		Device Frequency (F_OSC)
ADC Clock Source	ADCLK	64 MHz	32 MHz	20 MHz	16 MHz	8 MHz	4 MHz	1 MHz
F_OSC/2	000000	31.25 ns⁽²⁾	62.5 ns⁽²⁾	100 ns⁽²⁾	125 ns⁽²⁾	250 ns⁽²⁾	500 ns⁽²⁾	2.0 μs
F_OSC/4	000001	62.5 ns⁽²⁾	125 ns⁽²⁾	200 ns⁽²⁾	250 ns⁽²⁾	500 ns⁽²⁾	1.0 μs	4.0 μs
F_OSC/6	000010	125 ns⁽²⁾	187.5 ns⁽²⁾	300 ns⁽²⁾	375 ns⁽²⁾	750 ns⁽²⁾	1.5 μs	6.0 μs
F_OSC/8	000011	187.5 ns⁽²⁾	250 ns⁽²⁾	400 ns⁽²⁾	500 ns⁽²⁾	1.0 μs	2.0 μs	8.0 μs⁽³⁾
...	...	...	...	...	...	...	...	...
F_OSC/16	000100	250 ns⁽²⁾	500 ns⁽²⁾	800 ns⁽²⁾	1.0 μs	2.0 μs	4.0 μs	16.0 μs⁽³⁾
...	...	...	...	...	...	...	...	...
F_OSC/128	111111	2.0 μs	4.0 μs	6.4 μs	8.0 μs	16.0 μs⁽³⁾	32.0 μs⁽²⁾	128.0 μs⁽²⁾
FRC	ADCS=1	1.0-6.0 μs	1.0-6.0 μs	1.0-6.0 μs	1.0-6.0 μs	1.0-6.0 μs	1.0-6.0 μs	1.0-6.0 μs
Note: 1.See T_AD parameter in the "Electrical Specifications" section for FRC source typical T_AD value. 2.These values violate the required T_AD time. 3.Outside the recommended T_AD time. 4.The ADC clock period (T_AD) and total ADC conversion time can be minimized when the ADC clock is derived from the system clock F_OSC. However, the FRC oscillator source must be used when conversions are to be performed with the device in Sleep mode.

Figure 1. Analog-to-Digital Conversion T_AD Cycles