Each I/O pin has an RxyPPS register with which the pin output source is selected. With few exceptions, the port TRIS control associated with that pin retains control over the pin output driver. Peripherals that control the pin output driver as part of the peripheral operation will override the TRIS control as needed. These peripherals include:
Although every pin has its own RxyPPS peripheral selection register, the selections are identical for every pin as shown in the following table.
| RxyPPS | Pin Rxy Output Source | PORT To Which Output Can Be Directed | |||||||
|---|---|---|---|---|---|---|---|---|---|
| 28-Pin Devices | 40-Pin Devices | ||||||||
| 0x17 | ADGRDB | A | — | C | A | — | C | — | — |
| 0x16 | ADGRDA | A | — | C | A | — | C | — | — |
| 0x15 | DSM | A | — | C | A | — | — | D | — |
| 0x14 | CLKR | — | B | C | — | B | C | — | — |
| 0x13 | TMR0 | — | B | C | — | B | C | — | — |
| 0x12 | MSSP2 (SDO/SDA) | — | B | C | — | B | — | D | — |
| 0x11 | MSSP2 (SCK/SCL) | — | B | C | — | B | — | D | — |
| 0x10 | MSSP1 (SDO/SDA) | — | B | C | — | B | C | — | — |
| 0x0F | MSSP1 (SCK/SCL) | — | B | C | — | B | C | — | — |
| 0x0E | CMP2 | A | — | C | A | — | — | — | E |
| 0x0D | CMP1 | A | — | C | A | — | — | D | — |
| 0x0C | EUSART2 (DT) | — | B | C | — | B | — | D | — |
| 0x0B | EUSART2 (TX/CK) | — | B | C | — | B | — | D | — |
| 0x0A | EUSART1 (DT) | — | B | C | — | B | C | — | — |
| 0x09 | EUSART1 (TX/CK) | — | B | C | — | B | C | — | — |
| 0x08 | PWM4 | A | — | C | A | — | C | — | — |
| 0x07 | PWM3 | A | — | C | A | — | — | D | — |
| 0x06 | CCP2 | — | B | C | — | B | C | — | — |
| 0x05 | CCP1 | — | B | C | — | B | C | — | — |
| 0x04 | CWG1D | — | B | C | — | B | C | — | — |
| 0x03 | CWG1C | — | B | C | — | B | — | D | — |
| 0x02 | CWG1B | — | B | C | — | B | — | D | — |
| 0x01 | CWG1A | — | B | C | — | B | C | — | — |
| 0x00 | LATxy | A | B | C | A | B | C | D | E |