| ADDFSR | Add Literal to FSR | |||
|---|---|---|---|---|
| Syntax: | ADDFSR f, k | |||
| Operands: | 0 ≤ k ≤ 63 f ∈ [ 0, 1, 2 ] |
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| Operation: | FSR(f) + k → FSR(f) | |||
| Status Affected: | None | |||
| Encoding: | 1110 | 1000 | ffkk | kkkk |
| Description: | The 6-bit literal ‘k’ is added to the contents of the FSR specified by ‘f’. | |||
| Words: | 1 | |||
| Cycles: | 1 | |||
| Q Cycle Activity: | ||||
| Q1 | Q2 | Q3 | Q4 | |
| Decode | Read literal ‘k’ | Process Data | Write to FSR | |
| Example: | ADDFSR 2, 23h | |||
| Before Instruction FSR2 = 03FFh After Instruction FSR2 = 0422h |
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| ADDULNK | Add Literal to FSR2 and Return | |||
|---|---|---|---|---|
| Syntax: | ADDULNK k | |||
| Operands: | 0 ≤ k ≤ 63 | |||
| Operation: | FSR2 + k → FSR2, | |||
| (TOS) → PC | ||||
| Status Affected: | None | |||
| Encoding: | 1110 | 1000 | 11kk | kkkk |
| Description: | The 6-bit literal ‘k’ is added to the contents of FSR2. A RETURN is then
executed by loading the PC with the TOS. The
instruction takes two cycles to execute; a This may be thought of as a special case of the ADDFSR instruction, where f = 3 (binary ‘11’); it operates only on FSR2. |
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| Words: | 1 | |||
| Cycles: | 2 | |||
| Q Cycle Activity: | ||||
| Q1 | Q2 | Q3 | Q4 | |
| Decode | Read literal ‘k’ | Process Data | Write to FSR | |
| No Operation | No Operation | No Operation | No Operation | |
| Example: | ADDULNK 23h | |||
| Before Instruction FSR2 = 03FFh PC = 0100h After Instruction FSR2 = 0422h PC = (TOS) |
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| CALLW | Subroutine Call Using WREG | |||
|---|---|---|---|---|
| Syntax: | CALLW | |||
| Operands: | None | |||
| Operation: | (PC + 2) → TOS, (W) → PCL, (PCLATH) → PCH, (PCLATU) → PCU |
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| Status Affected: | None | |||
| Encoding: | 0000 | 0000 | 0001 | 0100 |
| Description | First, the return address (PC + 2) is pushed onto the return stack. Next, the
contents of W are written to PCL; the existing value is discarded. Then, the
contents of PCLATH and PCLATU are latched into PCH and PCU,
respectively. The
second cycle is
executed as a NOP instruction while the new
next instruction is fetched.Unlike CALL, there is no option to update W, Status or BSR. |
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| Words: | 1 | |||
| Cycles: | 2 | |||
| Q Cycle Activity: | ||||
| Q1 | Q2 | Q3 | Q4 | |
| Decode | Read WREG | PUSH PC to stack | No operation | |
| No operation | No operation | No operation | No operation | |
| Example: | |
|
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| Before Instruction PC = address (HERE) PCLATH = 10h PCLATU = 00h W = 06h After Instruction PC = 001006h TOS = address (HERE + 2) PCLATH = 10h PCLATU = 00h W = 06h |
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| MOVSF | Move Indexed to f | |||
|---|---|---|---|---|
| Syntax: | MOVSF [zs], fd | |||
| Operands: | 0 ≤ zs ≤ 127 0 ≤ fd ≤ 4095 |
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| Operation: | ((FSR2) + zs) → fd | |||
| Status Affected: | None | |||
| Encoding: 1st word (source) 2nd word (destin.) |
1110 1111 |
1011 ffff |
0zzz ffff |
zzzzs ffffd |
| Description: | The contents of the source register are moved to destination register ‘fd’. The actual address of the source register
is determined by adding the 7-bit literal offset ‘zs’ in the first word to the value of FSR2. The address of the
destination register is specified by the 12-bit literal ‘fd’ in the second word. Both addresses can be
anywhere in the 4096-byte data space (000h to FFFh). The If the resultant source address points to an indirect addressing register, the value returned will be 00h. |
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| Words: | 2 | |||
| Cycles: | 2 | |||
| Q Cycle Activity: | ||||
| Q1 | Q2 | Q3 | Q4 | |
| Decode | Determine source addr | Determine source addr | Read source reg | |
| Decode | No
operation No dummy read |
No operation | Write register ‘f’ (dest) | |
| Example: | |
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| Before Instruction FSR2 = 80h Contents of 85h = 33h REG2 = 11h After Instruction FSR2 = 80h Contents of 85h = 33h REG2 = 33h |
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| MOVSS | Move Indexed to Indexed | |||
|---|---|---|---|---|
| Syntax: | MOVSS [zs], [zd] | |||
| Operands: | 0 ≤ zs ≤ 127 0 ≤ zd ≤ 127 |
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| Operation: | ((FSR2) + zs) → ((FSR2) + zd) | |||
| Status Affected: | None | |||
| Encoding: 1st word (source) 2nd word (dest.) |
1110 1111 |
1011 xxxx |
1zzz xzzz |
zzzzs zzzzd |
| Description | The contents of the source register are moved to the destination register. The
addresses of the source and destination registers are determined by adding the
7-bit literal offsets ‘zs’ or ‘zd’,
respectively, to the value of FSR2. Both
registers can be located anywhere in the 4096-byte data memory space (000h to
FFFh). The MOVSS instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. If the resultant source address points to an indirect addressing register,
the value returned will be 00h. If the
resultant destination address points
to an indirect addressing register, the instruction will execute as a
|
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| Words: | 2 | |||
| Cycles: | 2 | |||
| Q Cycle Activity: | ||||
| Q1 | Q2 | Q3 | Q4 | |
| Decode | Determine source addr | Determine source addr | Read source reg | |
| Decode | Determine dest addr | Determine dest addr | Write to dest reg | |
| Example: | |
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| Before Instruction FSR2 = 80h Contents of 85h = 33h Contents of 86h = 11h After Instruction FSR2 = 80h Contents of 85h = 33h Contents of 86h = 33h |
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| PUSHL | Store Literal at FSR2, Decrement FSR2 | |||
|---|---|---|---|---|
| Syntax: | PUSHL k | |||
| Operands: | 0 ≤ k ≤ 255 | |||
| Operation: | k → (FSR2), FSR2 – 1 → FSR2 |
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| Status Affected: | None | |||
| Encoding: | 1111 | 1010 | kkkk | kkkk |
| Description: | The 8-bit literal ‘k’ is written to the data memory address specified by FSR2. FSR2 is decremented by 1 after the operation. This instruction allows users to push values onto a software stack. |
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| Words: | 1 | |||
| Cycles: | 1 | |||
| Q Cycle Activity: | ||||
| Q1 | Q2 | Q3 | Q4 | |
| Decode | Read ‘k’ | Process data | Write to destination | |
| Example: | |
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| Before Instruction FSR2H:FSR2L = 01ECh Memory (01ECh) = 00h After Instruction FSR2H:FSR2L = 01EBh Memory (01ECh) = 08h |
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| SUBFSR | Subtract Literal from FSR | |||
|---|---|---|---|---|
| Syntax: | SUBFSR f, k | |||
| Operands: | 0 ≤ k ≤ 63 | |||
| f ∈ [ 0, 1, 2 ] | ||||
| Operation: | FSR(f) – k → FSRf | |||
| Status Affected: | None | |||
| Encoding: | 1110 | 1001 | ffkk | kkkk |
| Description: | The 6-bit literal ‘k’ is subtracted from the contents of the FSR specified by ‘f’. | |||
| Words: | 1 | |||
| Cycles: | 1 | |||
| Q Cycle Activity: | ||||
| Q1 | Q2 | Q3 | Q4 | |
| Decode | Read register ‘f’ | Process Data | Write to destination | |
| Example: | SUBFSR 2, 23h | |||
| Before Instruction FSR2 = 03FFh After Instruction FSR2 = 03DCh |
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| SUBULNK | Subtract Literal from FSR2 and Return | |||
|---|---|---|---|---|
| Syntax: | SUBULNK k | |||
| Operands: | 0 ≤ k ≤ 63 | |||
| Operation: | FSR2 – k → FSR2 | |||
| (TOS) → PC | ||||
| Status Affected: | None | |||
| Encoding: | 1110 | 1001 | 11kk | kkkk |
| Description: | The 6-bit literal ‘k’ is subtracted from the contents of the FSR2. A RETURN is
then executed by loading the PC with the TOS. The
instruction takes two cycles to
execute; a This may be thought of as a special case of the SUBFSR instruction, where f = 3 (binary ‘11’); it operates only on FSR2. |
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| Words: | 1 | |||
| Cycles: | 2 | |||
| Q Cycle Activity: | ||||
| Q1 | Q2 | Q3 | Q4 | |
| Decode | Read register ‘f’ | Process Data | Write to destination | |
| No Operation | No Operation | No Operation | No Operation | |
| Example: | SUBULNK 23h | |||
| Before Instruction FSR2 = 03FFh PC = 0100h After Instruction FSR2 = 03DCh PC = (TOS) |
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