Low-power Features

Main Voltage Regulator Selection

The main voltage regulator can operate from two different internal regulators; LDO or buck regulator. The buck regulator is the most power efficient and is used in this example. The voltage regulator can be switched on the fly by writing to the Voltage Regulator Selection bit in the Voltage Regulator System Control register (VREG.SEL), shown in the below code snippet.

SUPC->VREG.bit.SEL = 1;

Enable Voltage Reference in Standby

The voltage reference used for the ADC conversion should be available in sleep modes but only when requested. It is therefore necessary to set the Run in Standby bit and the On Demand Control bit in the Voltage References System Control register (VREF.RUNSTDBY/ONDEMAND), shown in the below code snippet.


Enable Voltage Regulator in Standby

The ADC will require a voltage regulator capable of delivering an output sufficient for conversions. The main voltage regulator is therefore preferred also in Standby sleep mode where a low-power voltage regulator (LPVREG) is selected by default. To enable the main voltage regulator in Standby sleep mode the Run in Standby bit in the Voltage Regulator System Conrol register (VREG.RUNSTDBY) must be set.


Enable Dynamic Power Domain Gating

Power domain gating allows the device to power only selected parts of the device. In Standby sleep mode, domains containing solely disabled peripherals will by default be in retention state to reduce current leakage and thereby lower the power consumption. Domains containing enabled peripherals can dynamically switch between active and retention state depending on the state of the peripherals. This feature is controlled by the Dynamic Power Domain Gating for Power Domain x bits in the Standby Configuration register (STDBYCFG.DPGPDx), which must be set to allow dynamic switching. In the example project, dynamic power domain gating is enabled for PD0 containing e.g. ADC and OSCCTRL, and also enabled for PD1 containing e.g. DMAC. Enabling dynamic switching of PD0 and PD1 is shown in the below code snippet. In the example project, enabling dynamic power domain gating reduces the average power consumption by ~35μA.


Clock Configurations and Performance Level Selection

The performance level technique consists of adjusting the voltage of the regulator output to reduce power consumption. Performance levels are automatically selected depending on main clock frequency. By selecting GCLK generator frequencies below 24MHz and both CPU and peripheral clock frequencies below 12MHz, the device will operate at the lowest and most power efficient performance level PL0. In the example project, the main frequency is 4MHz. Clock settings are configured in conf_clocks.h:

/* SYSTEM_CLOCK_SOURCE_OSC16M configuration - Internal 16MHz oscillator */
/* Configure GCLK generator 0 (Main Clock) */
#  define CONF_CLOCK_GCLK_0_ENABLE          true

Ultra-Low-Power Oscillator Selection

The ultra-low-power internal 32.768kHz oscillator OSCULP32K provides the device with the lowest oscillator power consumption. OSCULP32K is enabled by default and should be preferred whenever the power requirements are prevalent over frequency stability and accuracy. In the example project, OSCULP32K is applied as RTC clock source, as defined in conf_rtc.h:


Enable Sleepwalking

Sleepwalking allows a peripheral to wake up its corresponding GCLK and run while the device is in a sleep mode, without waking up the CPU. To perform a sleepwalking task a peripheral should be configured to run on demand in standby. This will allow the peripheral to run only when requested. For the ADC these settings are configured by setting the On Demand Control bit and the Run in Standby bit in the Control A register (CTRLA.ONDEMAND/RUNSTDBY). The corresponding clock source should also run on demand, to ensure it is only awake when requested by a peripheral. The OSC16M will by default run only on demand when in Standby sleep mode.